# File: mkstr.src
#
program "%Z% MODULE: %M% RELEASE: %R%.%L% CREATED: %G% %U%"
source "mkstr.ips"
#
# DSBQUE                ; Disable Queue
tcblock mbipldin 0x0154 
#
#=======================================================
#
#
#;===================================================
#; MDI 30 second Prime Data Products Construction Program 
#;
#; This file contains modules to construct lo rate
#; data products.
#;
#; Regsiter Usage:
#;    R0081 - HR TLM board state
#;   
#; Note: Prior to invoking this program, 
#;                 i) request 5k telemetry (req sci5k), 
#;                ii) enable DEP interrupts (ENBIRPT - 0x134) and 
#;               iii) set DEP mode to 3 (mbdpmod 3).
#;---------------------------------------------------
#;
#; V1.0 -  9 Aug 95
#;      Constructed from the 60 second version (1.0).
#;
#; V1.1 - 23 Aug 95
#;      High Rate TLM handling
#;---------------------------------------------------
#STR60::
#    GOTOREG    $IPRL_STR_EP60
tcblock mbipcmd 0x0091 0x0100   0x0158 0x04BC 
#;
#INIT60:
#    CALLQUE    &INITDATA
tcblock mbipcmd 0x0091 0x0102   0x01F8 0x0652 
#    CALLQUE    &INITREGL
tcblock mbipcmd 0x0091 0x0104   0x01F8 0x047B 
#    SETREG     $IPRL_STR_EP60     &SETPTR60
tcblock mbipcmd 0x0091 0x0106   0x0140 0x04BC 0x010C 
#    SETREG     $IPRL_STR_STRT60   &SETPTR60
tcblock mbipcmd 0x0091 0x0109   0x0140 0x04F4 0x010C 
#;
#SETPTR60:
#    SETREG     $IPRL_STR_VELXFR   $IPRL_STR_VEL60
tcblock mbipcmd 0x0091 0x010C   0x0140 0x04C6 0x04C7 
#    SETREG     $IPRL_STR_LDXFR    $IPRL_STR_LD60
tcblock mbipcmd 0x0091 0x010F   0x0140 0x04E0 0x04E1 
#    SETREG     $IPRL_STR_EP60     &CKFRM60
tcblock mbipcmd 0x0091 0x0112   0x0140 0x04BC 0x0115 
#;
#CKFRM60:
#    BRANCHEQ   R3072   1  &FRM01
tcblock mbipcmd 0x0091 0x0115   0x01AE 0x0C00 0x0001 0x0167 
#    BRANCHEQ   R3072   2  &FRM02
tcblock mbipcmd 0x0091 0x0119   0x01AE 0x0C00 0x0002 0x0172 
#    BRANCHEQ   R3072   4  &FRM04
tcblock mbipcmd 0x0091 0x011D   0x01AE 0x0C00 0x0004 0x0177 
#    BRANCHEQ   R3072   5  &FRM05
tcblock mbipcmd 0x0091 0x0121   0x01AE 0x0C00 0x0005 0x018A 
#    BRANCHEQ   R3072   7  &FRM07
tcblock mbipcmd 0x0091 0x0125   0x01AE 0x0C00 0x0007 0x0197 
#    BRANCHEQ   R3072  19  &FRM19  ; 
tcblock mbipcmd 0x0091 0x0129   0x01AE 0x0C00 0x0013 0x019D 
#    BRANCHEQ   R3072  20  &FRM20
tcblock mbipcmd 0x0091 0x012D   0x01AE 0x0C00 0x0014 0x01D7 
#
#    END
tcblock mbipcmd 0x0091 0x0131   0x01FC 
#;
#;................................................................
#;
#STR30::
#    GOTOREG    $IPRL_STR_EP30
tcblock mbipcmd 0x0091 0x0132   0x0158 0x04BD 
#;
#INIT30:
#    CALLQUE    &INITDATA
tcblock mbipcmd 0x0091 0x0134   0x01F8 0x0652 
#    CALLQUE    &INITREGL
tcblock mbipcmd 0x0091 0x0136   0x01F8 0x047B 
#    SETREG     $IPRL_STR_EP30     &SETPTR30
tcblock mbipcmd 0x0091 0x0138   0x0140 0x04BD 0x013E 
#    SETREG     $IPRL_STR_STRT30   &SETPTR30
tcblock mbipcmd 0x0091 0x013B   0x0140 0x04F3 0x013E 
#;
#SETPTR30:
#    SETREG     $IPRL_STR_VELXFR   $IPRL_STR_VEL30
tcblock mbipcmd 0x0091 0x013E   0x0140 0x04C6 0x04CF 
#    SETREG     $IPRL_STR_LDXFR    $IPRL_STR_LD30
tcblock mbipcmd 0x0091 0x0141   0x0140 0x04E0 0x04EA 
#    SETREG     $IPRL_STR_EP30     &CKFRM30
tcblock mbipcmd 0x0091 0x0144   0x0140 0x04BD 0x0147 
#;
#CKFRM30:
#    BRANCHEQ   R3072   1  &FRM01
tcblock mbipcmd 0x0091 0x0147   0x01AE 0x0C00 0x0001 0x0167 
#    BRANCHEQ   R3072   2  &FRM02
tcblock mbipcmd 0x0091 0x014B   0x01AE 0x0C00 0x0002 0x0172 
#    BRANCHEQ   R3072   4  &FRM04
tcblock mbipcmd 0x0091 0x014F   0x01AE 0x0C00 0x0004 0x0177 
#    BRANCHEQ   R3072   5  &FRM05
tcblock mbipcmd 0x0091 0x0153   0x01AE 0x0C00 0x0005 0x018A 
#    BRANCHEQ   R3072   7  &FRM07
tcblock mbipcmd 0x0091 0x0157   0x01AE 0x0C00 0x0007 0x0197 
#    BRANCHEQ   R3072   9  &FRM09   
tcblock mbipcmd 0x0091 0x015B   0x01AE 0x0C00 0x0009 0x019D 
#    BRANCHEQ   R3072  10  &FRM10
tcblock mbipcmd 0x0091 0x015F   0x01AE 0x0C00 0x000A 0x01A2 
#
#    END
tcblock mbipcmd 0x0091 0x0163   0x01FC 
#;
#;................................................
#CALLBACK::
#    GOTOREG    R3104
tcblock mbipcmd 0x0091 0x0164   0x0158 0x0C20 
#    RTNQUE
tcblock mbipcmd 0x0091 0x0166   0x01FA 
#;................................................
#FRM01:
#;
#    SETREG     R143  16
tcblock mbipcmd 0x0091 0x0167   0x0140 0x008F 0x0010 
#    PURGELST   R136
tcblock mbipcmd 0x0091 0x016A   0x0190 0x0088 
#    SETREG     R135  16
tcblock mbipcmd 0x0091 0x016C   0x0140 0x0087 0x0010 
#    PURGETAB   R128
tcblock mbipcmd 0x0091 0x016F   0x0194 0x0080 
#;
#    END
tcblock mbipcmd 0x0091 0x0171   0x01FC 
#;................................................
#FRM02:
#    AVGTEMPS   3:0x00134  12
tcblock mbipcmd 0x0091 0x0172   0x0186 0x0134 0x1800 0x000C 
#    END
tcblock mbipcmd 0x0091 0x0176   0x01FC 
#;................................................
#FRM04:
#;  If HR board hang problem has been detected at 
#;frame 20, reset the IP here and re-start the 
#;downlink. A reset at this point allows at least
#;the full velocity image to be downlinked. The
#;last part of the continuum image however will 
#;still be lost.
#;  This code should execute if 
#;      in dynamics mode
#;      HR problem detected at Frame 20.
#;
#    BRANCHIF  R3077   &DONE04   ; skip if not in Dynamics
tcblock mbipcmd 0x0091 0x0177   0x015A 0x0C05 0x0186 
#    BRANCHNR  0x4000  &DONE04
tcblock mbipcmd 0x0091 0x017A   0x01A6 0x4000 0x0186 
#    BRANCHEQ  R0081   0    &DONE04
tcblock mbipcmd 0x0091 0x017D   0x01AE 0x0051 0x0000 0x0186 
#    SAVEMODE
tcblock mbipcmd 0x0091 0x0181   0x01E6 
#    SETREG    R0082   1
tcblock mbipcmd 0x0091 0x0182   0x0140 0x0052 0x0001 
#    END
tcblock mbipcmd 0x0091 0x0185   0x01FC 
#DONE04:
#    SETREG    R0082   0
tcblock mbipcmd 0x0091 0x0186   0x0140 0x0052 0x0000 
#    END
tcblock mbipcmd 0x0091 0x0189   0x01FC 
#;................................................
#FRM05:
#    BRANCHIF  R0082   &DONE05
tcblock mbipcmd 0x0091 0x018A   0x015A 0x0052 0x0193 
#    START2HR  0x49  0x4000  0x4800  R518  R534
tcblock mbipcmd 0x0091 0x018D   0x019A 0x0049 0x4000 0x4800 \
                                0x0206 0x0216 
#DONE05:
#    SETREG    R0082   0
tcblock mbipcmd 0x0091 0x0193   0x0140 0x0052 0x0000 
#    END
tcblock mbipcmd 0x0091 0x0196   0x01FC 
#;................................................
#FRM07:
#    SAVEMODE   
tcblock mbipcmd 0x0091 0x0197   0x01E6 
#    COPYTAB    R1116             ; Copy Vel Table
tcblock mbipcmd 0x0091 0x0198   0x01B4 0x045C 
#    COPYTAB    R1124             ; Copy Reciprocal Table
tcblock mbipcmd 0x0091 0x019A   0x01B4 0x0464 
#    END
tcblock mbipcmd 0x0091 0x019C   0x01FC 
#;
#;................................................
#FRM19:
#FRM09:
#    CALLQUE    &MKVEL
tcblock mbipcmd 0x0091 0x019D   0x01F8 0x01ED 
#    CALLQUE    &MKLDPTH
tcblock mbipcmd 0x0091 0x019F   0x01F8 0x01F4 
#    END
tcblock mbipcmd 0x0091 0x01A1   0x01FC 
#;................................................
#FRM10:
#    LRDINIT    0
tcblock mbipcmd 0x0091 0x01A2   0x018E 0x0000 
#    CALLQUE    &MKCNTNM
tcblock mbipcmd 0x0091 0x01A4   0x01F8 0x01FB 
#;
#    BRANCHEQ   R3076    1   &SETCF  ; Cmpg Mode; Skip V+Ic D/L 
tcblock mbipcmd 0x0091 0x01A6   0x01AE 0x0C04 0x0001 0x01D1 
#    BRANCHIF   $IPRF_STR_CF &CHKALT
tcblock mbipcmd 0x0091 0x01AA   0x015A 0x05A9 0x01B2 
#    SETREG     $IPRF_STR_CF 0
tcblock mbipcmd 0x0091 0x01AD   0x0140 0x05A9 0x0000 
#    GOTO       &DO5K
tcblock mbipcmd 0x0091 0x01B0   0x0156 0x01D4 
#;
#; The state of flags is preserved for ALT repeats
#CHKALT:
#    BRANCHNE   $IPRL_STR_COUNT  0   &CHKFLG 
tcblock mbipcmd 0x0091 0x01B2   0x01B0 0x0544 0x0000 0x01C2 
#    COPYREG    $IPRL_STR_ALTRPTS    $IPRL_STR_COUNT  
tcblock mbipcmd 0x0091 0x01B6   0x0142 0x0545 0x0544 
#    ADDREGD    $IPRL_STR_COUNT      1
tcblock mbipcmd 0x0091 0x01B9   0x01BC 0x0544 0x0001 
#    COPYREG    R3075    $IPRL_STR_VC
tcblock mbipcmd 0x0091 0x01BC   0x0142 0x0C03 0x0546 
#    COPYREG    R3077    $IPRL_STR_MAGHR
tcblock mbipcmd 0x0091 0x01BF   0x0142 0x0C05 0x0547 
#;
#CHKFLG:
#    ADDREGD    $IPRL_STR_COUNT   0xFFFF
tcblock mbipcmd 0x0091 0x01C2   0x01BC 0x0544 0xFFFF 
#    BRANCHEQ   R3075    0   &DO5K   ; skip hi rate D/L if VC = 0
tcblock mbipcmd 0x0091 0x01C5   0x01AE 0x0C03 0x0000 0x01D4 
#    BRANCHEQ   R3077    1   &DO5K   ; MAG D/L in 160K
tcblock mbipcmd 0x0091 0x01C9   0x01AE 0x0C05 0x0001 0x01D4 
#;
#    CALLQUE    &DMPHR
tcblock mbipcmd 0x0091 0x01CD   0x01F8 0x037F 
#    GOTO       &DO5K
tcblock mbipcmd 0x0091 0x01CF   0x0156 0x01D4 
#;
#SETCF:
#    SETREG     $IPRF_STR_CF   1
tcblock mbipcmd 0x0091 0x01D1   0x0140 0x05A9 0x0001 
#;
#DO5K:
#    CALLQUE    &STRDPS
tcblock mbipcmd 0x0091 0x01D4   0x01F8 0x0227 
#    END
tcblock mbipcmd 0x0091 0x01D6   0x01FC 
#;................................................
#FRM20:
#    LRDINIT    0
tcblock mbipcmd 0x0091 0x01D7   0x018E 0x0000 
#    CALLQUE    &MKCNTNM
tcblock mbipcmd 0x0091 0x01D9   0x01F8 0x01FB 
#    BRANCHIF   R3075    &DP5K           ; skip hi rate if VC = 0
tcblock mbipcmd 0x0091 0x01DB   0x015A 0x0C03 0x01EA 
#    BRANCHIF   $IPRF_MAG_HR    &V_I_DL  ; D/L stored mags if IPRF
tcblock mbipcmd 0x0091 0x01DE   0x015A 0x05A8 0x01E8 
#    CALLQUE    &QSR_MAG_HRDL
tcblock mbipcmd 0x0091 0x01E1   0x01F8 0x0C00 
#    BRANCHIF   $IPRF_MAG_HR    &V_I_DL  ; If all mags done, d/l v
tcblock mbipcmd 0x0091 0x01E3   0x015A 0x05A8 0x01E8 
#    GOTO       &DP5K
tcblock mbipcmd 0x0091 0x01E6   0x0156 0x01EA 
#V_I_DL:
#    CALLQUE    &DMPHR
tcblock mbipcmd 0x0091 0x01E8   0x01F8 0x037F 
#DP5K:
#    CALLQUE    &STRDPS
tcblock mbipcmd 0x0091 0x01EA   0x01F8 0x0227 
#    END
tcblock mbipcmd 0x0091 0x01EC   0x01FC 
#;................................................
#;
#MKVEL:
#; Velocity:
#;       Source Page Sa   : Page 0, Offset 1300
#;       Source Page Sc   : Page 1, Offset 1300
#;       Destination Page : Page 5, Offset 0
#;       Shift Count      :  3  (Sum of 4 images)
#;       Block Count      :  127
#;
#;
#;   SETREGS    R800     8   0:0x00514  1:0x00514  5:0x00000  3 12
#;
#    COPYRI2D   $IPRL_STR_VELXFR  $IPRL_STR_VELWRK  $#IPRL_STR_VEL
tcblock mbipcmd 0x0091 0x01ED   0x01AC 0x04C6 0x04BE 0x0008 
#    VLCTY      $IPRL_STR_VELWRK
tcblock mbipcmd 0x0091 0x01F1   0x017C 0x04BE 
#    RTNQUE
tcblock mbipcmd 0x0091 0x01F3   0x01FA 
#;
#;.......................
#;
#MKLDPTH:
#;
#; Line Depth:
#;       Source Page Sa   : Page 0, Offset 1300
#;       Source Page Sc   : Page 1, Offset 1300
#;       Destination Page : Page 6, Offset 0
#;       Shift Count      :  16  
#;       Block Count      : 127 (Process data per call ~150ms)
#;       Lookup Seqgment  :  9  (Depends on SQRT table location)
#;
#;   SETREGS   R808 9  0:0x00514  1:0x00514  6:0x00000  16  127  9
#;
#    COPYRI2D  $IPRL_STR_LDXFR  $IPRL_STR_LDWRK  $#IPRL_STR_LDWRK
tcblock mbipcmd 0x0091 0x01F4   0x01AC 0x04E0 0x04D7 0x0009 
#    LDEPTH    $IPRL_STR_LDWRK
tcblock mbipcmd 0x0091 0x01F8   0x017E 0x04D7 
#;
#    RTNQUE
tcblock mbipcmd 0x0091 0x01FA   0x01FA 
#;
#;.....................................................
#;      
#MKCNTNM:
#;
#; Continuum:
#;
#; Extract 1024^2 Sd from page 2 to page 1 
#;      Source Page       : page 2, Offset 1300
#;      Destination       : Page 1, Offset 0
#;      X-Length          : 1024
#;      Y-Length          : 1024
#;      Row Length        : 1040
#;      Global Offset Reg.:   69
#;
#    SETREGS  R811  8   2:0x00514 1:0x00000  1024  1024  1040  69
tcblock mbipcmd 0x0091 0x01FB   0x01B2 0x032B 0x0008 0x0514 \
                                0x1000 0x0000 0x0800 0x0400 \
                                0x0400 0x0410 0x0045 
#    EXTRACT  R811
tcblock mbipcmd 0x0091 0x0206   0x017A 0x032B 
#;
#;   Extract 1024^2 Si from page 3 to page 4
#;      Source Page       : page 3, Offset 1300
#;      Destination       : Page 4, Offset 0
#;      X-Length          : 1024
#;      Y-Length          : 1024
#;      Row Length        : 1040
#;      Global Offset Reg.:   69
#;
#    SETREGS  R819  8   1300 0x1800  0x0000 0x2000  1024  1024  10
tcblock mbipcmd 0x0091 0x0208   0x01B2 0x0333 0x0008 0x0514 \
                                0x1800 0x0000 0x2000 0x0400 \
                                0x0400 0x0410 0x0045 
#    EXTRACT  R819
tcblock mbipcmd 0x0091 0x0213   0x017A 0x0333 
#;
#;   Construct Continuum image in Page 7, from Sd, Si and Ld
#;     Source (Si)       : Page 4, Offset 0
#;     Source (Ld)       : Page 6, Offset 0
#;     Source (Sd)       : Page 1, Offset 0
#;     Destination       : Page 7, Offset 0
#;     Block Count       :  63 (1/2 image processed, each call < 3
#;     Cadc              : 200
#;
#    SETREGS  R821  10  4:0x00000 6:0x00000 1:0x00000 7:0x00000 63
tcblock mbipcmd 0x0091 0x0215   0x01B2 0x0335 0x000A 0x0000 \
                                0x2000 0x0000 0x3000 0x0000 \
                                0x0800 0x0000 0x3800 0x003F \
                                0x00C8 
#    CNTNM    R821
tcblock mbipcmd 0x0091 0x0222   0x0182 0x0335 
#    CNTNM    R821
tcblock mbipcmd 0x0091 0x0224   0x0182 0x0335 
#;
#    RTNQUE
tcblock mbipcmd 0x0091 0x0226   0x01FA 
#;
#;.......................
#;
#STRDPS:
#;
#MKMEDL: 
#; Construct Medium-l
#;
#; This routine assumes that X and Y vectors as well as a Vector w
#; bin list for Solar radius of 3264 units has already been loaded
#; 17:0x07000. Such a bin list consists of 29 bins generating 1450
#; data. 
#;
#; Construct vector weighted binned image  
#;  Velocity Page        5
#;  Destination Address  7:0x110000
#;  List Count           0
#;  List Count           6  (*5=30; 5 bins processed on last call)
#;  VWBIN List Address   17:0x07000
#;  Global Offset Reg.   69
#;
#; Velocity  -> Bad Pixel Removed  ->  Med-l
#;    5      ->        1           ->  7:0x110000
#;
#    COPYRD2D   R3052  R1092  8
tcblock mbipcmd 0x0091 0x0227   0x0144 0x0BEC 0x0444 0x0008 
#    BADPIX     R1092
tcblock mbipcmd 0x0091 0x022B   0x01D2 0x0444 
#;
#    COPYRD2D   R1072  R832   8
tcblock mbipcmd 0x0091 0x022D   0x0144 0x0430 0x0340 0x0008 
#    VWBIN      R832
tcblock mbipcmd 0x0091 0x0231   0x019E 0x0340 
#    VWBIN      R832
tcblock mbipcmd 0x0091 0x0233   0x019E 0x0340 
#    VWBIN      R832
tcblock mbipcmd 0x0091 0x0235   0x019E 0x0340 
#    VWBIN      R832
tcblock mbipcmd 0x0091 0x0237   0x019E 0x0340 
#    VWBIN      R832
tcblock mbipcmd 0x0091 0x0239   0x019E 0x0340 
#;
#;........................
#;
#MKGP:
#;
#; Construct Golf Proxy
#; (RWBinned Line Depth - 11289 pixels)
#;
#;
#    COPYRD2D   R3040  R1100  12
tcblock mbipcmd 0x0091 0x023B   0x0144 0x0BE0 0x044C 0x000C 
#    FLATFLD    R1100
tcblock mbipcmd 0x0091 0x023F   0x01CC 0x044C 
#;
#    COPYRD2D   R1024  R900  8
tcblock mbipcmd 0x0091 0x0241   0x0144 0x0400 0x0384 0x0008 
#    RWBIN      R900
tcblock mbipcmd 0x0091 0x0245   0x01A0 0x0384 
#    RWBIN      R900
tcblock mbipcmd 0x0091 0x0247   0x01A0 0x0384 
#    RWBIN      R900
tcblock mbipcmd 0x0091 0x0249   0x01A0 0x0384 
#;
#    COPYRD2D   R1032  R920  8
tcblock mbipcmd 0x0091 0x024B   0x0144 0x0408 0x0398 0x0008 
#    RWBIN      R920
tcblock mbipcmd 0x0091 0x024F   0x01A0 0x0398 
#    RWBIN      R920
tcblock mbipcmd 0x0091 0x0251   0x01A0 0x0398 
#    RWBIN      R920
tcblock mbipcmd 0x0091 0x0253   0x01A0 0x0398 
#;
#;..........................
#;
#MKFB:
#;
#; Construct Flux Budget 
#; (RWBinned Continuum)
#;                               
#    COPYRD2D   R3060  R1080  12
tcblock mbipcmd 0x0091 0x0255   0x0144 0x0BF4 0x0438 0x000C 
#    FLATFLD    R1080
tcblock mbipcmd 0x0091 0x0259   0x01CC 0x0438 
#
#    COPYRD2D   R1040  R952  8
tcblock mbipcmd 0x0091 0x025B   0x0144 0x0410 0x03B8 0x0008 
#    RWBIN      R952
tcblock mbipcmd 0x0091 0x025F   0x01A0 0x03B8 
#    RWBIN      R952
tcblock mbipcmd 0x0091 0x0261   0x01A0 0x03B8 
#    RWBIN      R952
tcblock mbipcmd 0x0091 0x0263   0x01A0 0x03B8 
#;
#    COPYRD2D   R1048  R972  8
tcblock mbipcmd 0x0091 0x0265   0x0144 0x0418 0x03CC 0x0008 
#    RWBIN      R972
tcblock mbipcmd 0x0091 0x0269   0x01A0 0x03CC 
#    RWBIN      R972
tcblock mbipcmd 0x0091 0x026B   0x01A0 0x03CC 
#    RWBIN      R972
tcblock mbipcmd 0x0091 0x026D   0x01A0 0x03CC 
#;
#;
#;...........................
#;
#MKLF:
#;
#; Construct Limb Figure
#;
#; Construct 1st Limb Figure from image in page 7 into page 6 (110
#    ;SETREGS   R856    8  0x5800   6:0x110000  0  2000 17:0x03000
#;   ;SETREGS   R856    8  0x3800   6:0x110000  0  2000 17:0x03000
#;
#    COPYRD2D  R1056  R856  8
tcblock mbipcmd 0x0091 0x026F   0x0144 0x0420 0x0358 0x0008 
#    CROP      R856
tcblock mbipcmd 0x0091 0x0273   0x0178 0x0358 
#;   TWAVG     R864
#;
#; Construct 2nd Limb Figure from image in page 7 into page 6 (114
#    ;SETREGS   R880    8  0x5000   6:0x115000  0  2000 17:0x05000
#    ;SETREGS   R880    8  0x3800   6:0x115000  0  2000 17:0x05000
#;
#    COPYRD2D  R1064  R880  8
tcblock mbipcmd 0x0091 0x0275   0x0144 0x0428 0x0370 0x0008 
#    CROP      R880
tcblock mbipcmd 0x0091 0x0279   0x0178 0x0370 
#;   TWAVG     R888
#;
#;
#    ; ADDREGD    R3583    2
#    ; GOTOREG    R3583
#;
#    GOTO      &SCITLM    ; Start 5k data downlink
tcblock mbipcmd 0x0091 0x027B   0x0156 0x027D 
#;
#;
#;--------------------------------------------------------
#; Program to downlink data via the 5k channel
#;
#;
#SCITLM:
#;
#; Structure Mode Telemetry output program
#; --------- ---- --------- ------ -------
#;  (Uses Registers R210-R293)
#;
#; Get System Time From Page 0
#;   LRDINIT  0x1800
#    NOOP
tcblock mbipcmd 0x0091 0x027D   0x01DE 
#    NOOP
tcblock mbipcmd 0x0091 0x027E   0x01DE 
#    NOOP
tcblock mbipcmd 0x0091 0x027F   0x01DE 
#    NOOP
tcblock mbipcmd 0x0091 0x0280   0x01DE 
#    NOOP
tcblock mbipcmd 0x0091 0x0281   0x01DE 
#;
#; Error log output (if needed)
#    COPYELOG  R464
tcblock mbipcmd 0x0091 0x0282   0x01EC 0x01D0 
#    BRANCHIF  R466  &MAG_DL
tcblock mbipcmd 0x0091 0x0284   0x015A 0x01D2 0x0289 
#    LRDXFR    R460
tcblock mbipcmd 0x0091 0x0287   0x0198 0x01CC 
#;
#;
#; Output Magnetogram if VC <> 0 && CmpgF == 0 && NSeg <> 0
#MAG_DL:
#    BRANCHIF  R3075                &ENDMAG            ; No 160k
tcblock mbipcmd 0x0091 0x0289   0x015A 0x0C03 0x02A3 
#    BRANCHEQ  R3076       1        &ENDMAG            ; Campaign 
tcblock mbipcmd 0x0091 0x028C   0x01AE 0x0C04 0x0001 0x02A3 
#    BRANCHIF  $IPRL_MAG_LRDPRM+3   &MED_L
tcblock mbipcmd 0x0091 0x0290   0x015A 0x0565 0x02B2 
#;
#    REGSUB    $IPRL_MAG_LRDPRM+13  $IPRL_MAG_LRDPRM+1  $IPRL_MAG_
tcblock mbipcmd 0x0091 0x0293   0x2146 0x056F 0x0563 0x057B 
#    BRANCHGT  $IPRL_MAG_TMP     0  &DO_MAG5K
tcblock mbipcmd 0x0091 0x0297   0x01BA 0x057B 0x0000 0x02A8 
#    REGSUB    $IPRL_MAG_LRDPRM+12  $IPRL_MAG_LRDPRM    $IPRL_MAG_
tcblock mbipcmd 0x0091 0x029B   0x2146 0x056E 0x0562 0x057B 
#    BRANCHGT  $IPRL_MAG_TMP     0  &DO_MAG5K
tcblock mbipcmd 0x0091 0x029F   0x01BA 0x057B 0x0000 0x02A8 
#ENDMAG:
#    SETREG    $IPRL_MAG_LRDPRM+3   0                  ; No more M
tcblock mbipcmd 0x0091 0x02A3   0x0140 0x0565 0x0000 
#    GOTO      &MED_L
tcblock mbipcmd 0x0091 0x02A6   0x0156 0x02B2 
#;
#DO_MAG5K:
#    LRDXFR    $IPRL_MAG_LRDPRM
tcblock mbipcmd 0x0091 0x02A8   0x0198 0x0562 
#    LRDXFR    $IPRL_MAG_LRDPRM
tcblock mbipcmd 0x0091 0x02AA   0x0198 0x0562 
#    LRDXFR    $IPRL_MAG_LRDPRM
tcblock mbipcmd 0x0091 0x02AC   0x0198 0x0562 
#    LRDXFR    $IPRL_MAG_LRDPRM
tcblock mbipcmd 0x0091 0x02AE   0x0198 0x0562 
#    GOTO      &MP2LRBUF
tcblock mbipcmd 0x0091 0x02B0   0x0156 0x02BE 
#;
#MED_L:
#;
#; Medium-l Data output
#;
#;   LRDXFR   R360
#;      NpixTotal          0
#;      NpixSeg            0
#;      Seqment            4
#;      Source             7:0x110000
#;      MaxSource          3584
#;      N                  0
#;      K                  0
#;      SegLength          3584
#;      DPID               0xBFFFFFB0L
#;      NPixImage          14336L
#;
#;   SETREGS  R360  9  0 0 0 4 7:0x110000 3584 0 0 
#;   SETREGS  R369  5 3584 0xBFFF 0xFFB0 14336 0
#    COPYRD2D R360  R472  16   ; Copy Med-l LRDXFR Registers
tcblock mbipcmd 0x0091 0x02B2   0x0144 0x0168 0x01D8 0x0010 
#    LRDXFR   R472
tcblock mbipcmd 0x0091 0x02B6   0x0198 0x01D8 
#    LRDXFR   R472
tcblock mbipcmd 0x0091 0x02B8   0x0198 0x01D8 
#    LRDXFR   R472
tcblock mbipcmd 0x0091 0x02BA   0x0198 0x01D8 
#    LRDXFR   R472
tcblock mbipcmd 0x0091 0x02BC   0x0198 0x01D8 
#;
#; GOLF Proxy
#MP2LRBUF:
#    LRDXFR   R374
tcblock mbipcmd 0x0091 0x02BE   0x0198 0x0176 
#;
#; Continuum Intensity
#;
#    LRDXFR   R388
tcblock mbipcmd 0x0091 0x02C0   0x0198 0x0184 
#;
#; Limb Figure
#;
#    LRDXFR   R402
tcblock mbipcmd 0x0091 0x02C2   0x0198 0x0192 
#;
#; LOI-v
#;      Source Page:          5
#;      Destination Addr.:    7:0x114740
#;      List Pointer:         0
#;      List Count:           5
#;      List Addr.:          17:0x030000
#;      Offset Reg:          69
#;
#    SETREGS  R1164 8 0x2800 7:0x114740 0 5 17:0x030000 R69
tcblock mbipcmd 0x0091 0x02C4   0x01B2 0x048C 0x0008 0x2800 \
                                0x4740 0x3811 0x0000 0x0005 \
                                0x0000 0x8803 0x0045 
#    IRBIN    R1164
tcblock mbipcmd 0x0091 0x02CF   0x01A4 0x048C 
#;
#;   Register List R416-R429 is initialized by Irregular Bin load
#;   command in the control file loi3b.src
#;
#    COPYRD2D R416  R1180  16
tcblock mbipcmd 0x0091 0x02D1   0x0144 0x01A0 0x049C 0x0010 
#    LRDXFR   R1180
tcblock mbipcmd 0x0091 0x02D5   0x0198 0x049C 
#;
#; LOI-c
#;      Source Page:          7
#;      Destination Addr.:    5:0x114920
#;      List Pointer:         0
#;      List Count:           5
#;      List Addr.:          17:0x030000
#;      Offset Reg:          69
#;
#;
#    SETREGS  R1172 8 0x3800 5:0x114920 0 5 17:0x030000 R69
tcblock mbipcmd 0x0091 0x02D7   0x01B2 0x0494 0x0008 0x3800 \
                                0x4920 0x2811 0x0000 0x0005 \
                                0x0000 0x8803 0x0045 
#    IRBIN    R1172
tcblock mbipcmd 0x0091 0x02E2   0x01A4 0x0494 
#;
#;   Register List R430-R443 is initialized by Irregular Bin load
#;   command in the control file loi3b.src
#;
#    COPYRD2D R430  R1196  16
tcblock mbipcmd 0x0091 0x02E4   0x0144 0x01AE 0x04AC 0x0010 
#    LRDXFR   R1196
tcblock mbipcmd 0x0091 0x02E8   0x0198 0x04AC 
#;
#; Register Block Data Product 
#;
#    CALLQUE  &REGDP
tcblock mbipcmd 0x0091 0x02EA   0x01F8 0x031A 
#;
#    LRDEND
tcblock mbipcmd 0x0091 0x02EC   0x0196 
#    SETIRPT  1
tcblock mbipcmd 0x0091 0x02ED   0x014E 0x0001 
#;
#;................................................................
#;
#; Construct Time Weighted Averages
#;
#    TWAVG    R908               ; MP #1
tcblock mbipcmd 0x0091 0x02EF   0x01CE 0x038C 
#    TWAVG    R928               ; MP #2
tcblock mbipcmd 0x0091 0x02F1   0x01CE 0x03A0 
#;
#    TWAVG    R960               ; FB #1
tcblock mbipcmd 0x0091 0x02F3   0x01CE 0x03C0 
#    TWAVG    R980               ; FB #2
tcblock mbipcmd 0x0091 0x02F5   0x01CE 0x03D4 
#;
#    TWAVG    R864               ; LF #1
tcblock mbipcmd 0x0091 0x02F7   0x01CE 0x0360 
#    TWAVG    R888               ; LF #2
tcblock mbipcmd 0x0091 0x02F9   0x01CE 0x0378 
#;
#;................................................................
#;
#    BRANCHEQ R873  0  &PATH1
tcblock mbipcmd 0x0091 0x02FB   0x01AE 0x0369 0x0000 0x0305 
#    BRANCHEQ R897  0  &PATH2
tcblock mbipcmd 0x0091 0x02FF   0x01AE 0x0381 0x0000 0x0309 
#    GOTO     &DONE5K
tcblock mbipcmd 0x0091 0x0303   0x0156 0x0319 
#;
#PATH1:
#;   _COPYLST R216                  ; MP RWBin 1 <- New MP RWBin L
#;   _COPYLST R280                  ; FB RWBin 1 <- New FB RWBin L
#    _COPYLST R344                  ; LFCropList1 <- New LF Crop L
tcblock mbipcmd 0x0091 0x0305   0x81C2 0x0158 
#    GOTO     &CPYLRD
tcblock mbipcmd 0x0091 0x0307   0x0156 0x030D 
#;
#PATH2:
#;   _COPYLST R224                  ; MP RWBin 2 <- New MP RWBin L
#;   _COPYLST R288                  ; FB RWBin 2 <- New FB RWBin L
#    _COPYLST R352                  ; LFCropList2 <- New LF Crop L
tcblock mbipcmd 0x0091 0x0309   0x81C2 0x0160 
#    GOTO     &CPYLRD
tcblock mbipcmd 0x0091 0x030B   0x0156 0x030D 
#;
#CPYLRD:
#    COPYRD2D R168  R374  14
tcblock mbipcmd 0x0091 0x030D   0x0144 0x00A8 0x0176 0x000E 
#    COPYRD2D R232  R388  14
tcblock mbipcmd 0x0091 0x0311   0x0144 0x00E8 0x0184 0x000E 
#    COPYRD2D R296  R402  14        ; Set LRDXFR from set 1
tcblock mbipcmd 0x0091 0x0315   0x0144 0x0128 0x0192 0x000E 
#;
#DONE5K:
#    RTNQUE
tcblock mbipcmd 0x0091 0x0319   0x01FA 
#;--------------------------------------------------------------
#; Function to create data product containing IP registers.
#;
#; Register Usage:
#;   Register(s)             Usage
#;     R1130        R_init:       Initialization Flag
#;     R1131        R_r0_addr_lo: Low order Address of R0
#;     R1132-1133   R_startaddr:  Address of 1st register of D/L B
#;     R1134        R_startnum:   Start register Number 
#;     R1135-1136   R_endaddr:    Address of last regsier of D/L B
#;     R1137        R_endnum:     End register number
#;     R1138        R_diff:       = (R_movreg - R_endaddr)
#;     R1139        R_movreg:     RL for moving a block of registe
#;     R1145        R_lrdxfr:     RL to create dp entry.
#;
#;   Address
#;    7:0x113C00    dp_buf0:      CCD Temperatures
#;    7:0x113C14    dp_buf1:      Fixed Registers (R126-R159)
#;    7:0x113C36    dp_buf2:      Register Block 
#;
#;     40           Count
#;     94           max_src
#;
#;................................................................
#;
#REGDP:
#    BRANCHIF  R1130        &MKDPC
tcblock mbipcmd 0x0091 0x031A   0x015A 0x046A 0x0325 
#;
#    CALLQUE   &INITREG
tcblock mbipcmd 0x0091 0x031D   0x01F8 0x0366 
#;   
#    SETREG    R1131        0xE000
tcblock mbipcmd 0x0091 0x031F   0x0140 0x046B 0xE000 
#;
#    SETREG    R1130        0
tcblock mbipcmd 0x0091 0x0322   0x0140 0x046A 0x0000 
#;
#MKDPC:
#;
#; Copy CCD temperatures to output buffer
#    SAVERLST  R0            20          7:0x113C00
tcblock mbipcmd 0x0091 0x0325   0x014A 0x0000 0x0014 0x3C00 \
                                0x3811 
#;
#; Copy current pointer in the register block to R126
#    REGSUB    R1140         R1131       R126
tcblock mbipcmd 0x0091 0x032A   0x2146 0x0474 0x046B 0x007E 
#;
#; Save Register pointer and Memory Purge registers to o/p buffer
#    SAVERLST  R126          34          7:0x113C14
tcblock mbipcmd 0x0091 0x032E   0x014A 0x007E 0x0022 0x3C14 \
                                0x3811 
#;
#; Set destination address in MOVBLKI register list
#    SETREGS   R1142      2              7:0x113C36
tcblock mbipcmd 0x0091 0x0333   0x01B2 0x0476 0x0002 0x3C36 \
                                0x3811 
#    SETREGS   R1144      2              40L   
tcblock mbipcmd 0x0091 0x0338   0x01B2 0x0478 0x0002 0x0028 \
                                0x0000 
#
#; Copy register sub-block and setup dpc header
#    MOVBLKI   R1140
tcblock mbipcmd 0x0091 0x033D   0x0166 0x0474 
#    SETREGS   R1146      6  0  0  0  1  7:0x113C00 
tcblock mbipcmd 0x0091 0x033F   0x01B2 0x047A 0x0006 0x0000 \
                                0x0000 0x0000 0x0001 0x3C00 \
                                0x3811 
#    SETREGS   R1152      6  94 0  0  94 0xcfff  0xffb6
tcblock mbipcmd 0x0091 0x0348   0x01B2 0x0480 0x0006 0x005E \
                                0x0000 0x0000 0x005E 0xCFFF \
                                0xFFB6 
#    SETREGS   R1158      2  94 0
tcblock mbipcmd 0x0091 0x0351   0x01B2 0x0486 0x0002 0x005E \
                                0x0000 
#    COPYREG   R126       R1157
tcblock mbipcmd 0x0091 0x0356   0x0142 0x007E 0x0485 
#    LRDXFR    R1146
tcblock mbipcmd 0x0091 0x0359   0x0198 0x047A 
#;
#; Check if Register block downlink is completed
#    REGSUB    R1140      R1136   R1160
tcblock mbipcmd 0x0091 0x035B   0x2146 0x0474 0x0470 0x0488 
#    BRANCHLT  R1160        0           &DONER
tcblock mbipcmd 0x0091 0x035F   0x01B8 0x0488 0x0000 0x0365 
#    CALLQUE   &INITREG
tcblock mbipcmd 0x0091 0x0363   0x01F8 0x0366 
#DONER:
#    RTNQUE
tcblock mbipcmd 0x0091 0x0365   0x01FA 
#;
#;.......................................................
#; Initialize Registers
#;
#; Registers area is 16:0x0BE000 to 16:0x0BFFFF
#;
#; R1134, R1135 - Contains the Register Block Start Number
#; R1138, R1139 - Contains Register Block End Number 
#; R1132, R1133 - Address of Start Register Number
#; R1135, R1136 - Address of end Register Number
#; R1140, R1141 - Address of next register to be downlinked
#;
#INITREG:
#    SETREGS   R1132   2             16:0x0BE000
tcblock mbipcmd 0x0091 0x0366   0x01B2 0x046C 0x0002 0xE000 \
                                0x800B 
#    ADDADR    R1132   R1134  R1132
tcblock mbipcmd 0x0091 0x036B   0x0148 0x046C 0x046E 0x046C 
#    SETREGS   R1136     2           16:0x0BE000
tcblock mbipcmd 0x0091 0x036F   0x01B2 0x0470 0x0002 0xE000 \
                                0x800B 
#    ADDADR    R1136   R1138  R1136
tcblock mbipcmd 0x0091 0x0374   0x0148 0x0470 0x0472 0x0470 
#    COPYREG   R1132   R1140
tcblock mbipcmd 0x0091 0x0378   0x0142 0x046C 0x0474 
#    COPYREG   R1133   R1141
tcblock mbipcmd 0x0091 0x037B   0x0142 0x046D 0x0475 
#    RTNQUE
tcblock mbipcmd 0x0091 0x037E   0x01FA 
#;.......................................................
#;--------------------------------------------------------------
#;           dmpdpc.ips
#;
#; This file contains modules to downlink Med-l, MP, FB
#; and LF data. 
#;
#;   R0081  -  High Rate Board Status; 0 = OK; 1 = NOK
#;
#;-----------------------------------------------------
#;...................................................
#;
#DMPHR:
#    BRANCHIF  $IPRF_MAG_HR      &STRTHR     ; MAG downlink active
tcblock mbipcmd 0x0091 0x037F   0x015A 0x05A8 0x0383 
#    RTNQUE
tcblock mbipcmd 0x0091 0x0382   0x01FA 
#;
#STRTHR:
#    BRANCHNR  0x4000  &HLTDL8   ; Page 8 is not available
tcblock mbipcmd 0x0091 0x0383   0x01A6 0x4000 0x0422 
#;
#VELIMG:
#    SETREGS  R512  6  1 0x0000  0x4000  0xE4  0xCFFF 0xFF25
tcblock mbipcmd 0x0091 0x0386   0x01B2 0x0200 0x0006 0x0001 \
                                0x0000 0x4000 0x00E4 0xCFFF \
                                0xFF25 
#    HRDINIT  R512
tcblock mbipcmd 0x0091 0x038F   0x019C 0x0200 
#;
#;   Load length in R518
#    COPYREG  R71  R518
tcblock mbipcmd 0x0091 0x0391   0x0142 0x0047 0x0206 
#    COPYREG  R72  R519
tcblock mbipcmd 0x0091 0x0394   0x0142 0x0048 0x0207 
#;   SETREGS  518  2  0xC0000L
#;
#; Scale Velocity data; Source Page 5, Dest Page 1
#    SETREGS  R504  8  5:0x00000  1:0x00000  0x100000L  1  16
tcblock mbipcmd 0x0091 0x0397   0x01B2 0x01F8 0x0008 0x0000 \
                                0x2800 0x0000 0x0800 0x0000 \
                                0x0010 0x0001 0x0010 
#    SCALE    R504
tcblock mbipcmd 0x0091 0x03A2   0x01BE 0x01F8 
#;
#;   Copy Velocity from page 1 to page 8
#    SETREGS  R520  8  0x0800   8:0x00226  0  1000  17:0x00000  R6
tcblock mbipcmd 0x0091 0x03A4   0x01B2 0x0208 0x0008 0x0800 \
                                0x0226 0x4000 0x0000 0x03E8 \
                                0x0000 0x8800 0x0045 
#    CROP     R520
tcblock mbipcmd 0x0091 0x03AF   0x0178 0x0208 
#;
#;.....................................................
#;
#IcIMG:
#    BRANCHNR  0x4800  &HLTDL9  ; Page 9 is not available
tcblock mbipcmd 0x0091 0x03B1   0x01A6 0x4800 0x0447 
#;
#Ic1:
#    SETREGS  R528  6  1 0x0000  0x4800  0xE2  0xCFFF 0xFF26
tcblock mbipcmd 0x0091 0x03B4   0x01B2 0x0210 0x0006 0x0001 \
                                0x0000 0x4800 0x00E2 0xCFFF \
                                0xFF26 
#    HRDINIT  R528
tcblock mbipcmd 0x0091 0x03BD   0x019C 0x0210 
#;
#;   Load length in R534
#    COPYREG  R71  R534
tcblock mbipcmd 0x0091 0x03BF   0x0142 0x0047 0x0216 
#    COPYREG  R72  R535
tcblock mbipcmd 0x0091 0x03C2   0x0142 0x0048 0x0217 
#;
#;   Crop Continuum from page 7 to page 4
#    SETREGS  R536  8  0x3800  4:0x00000  0  1000  17:0x00000  R69
tcblock mbipcmd 0x0091 0x03C5   0x01B2 0x0218 0x0008 0x3800 \
                                0x0000 0x2000 0x0000 0x03E8 \
                                0x0000 0x8800 0x0045 
#    CROP     R536
tcblock mbipcmd 0x0091 0x03D0   0x0178 0x0218 
#;   Apply Square-Root (Table @ Seg 9) scaling to the cropped imag
#    SETREGS  R544 8  4:0x00000  9:0x00226  0xC0000L  0x0000  9
tcblock mbipcmd 0x0091 0x03D2   0x01B2 0x0220 0x0008 0x0000 \
                                0x2000 0x0226 0x4800 0x0000 \
                                0x000C 0x0000 0x0009 
#    COPYREG  R71  R548
tcblock mbipcmd 0x0091 0x03DD   0x0142 0x0047 0x0224 
#    COPYREG  R72  R549
tcblock mbipcmd 0x0091 0x03E0   0x0142 0x0048 0x0225 
#    LOOKUP   R544
tcblock mbipcmd 0x0091 0x03E3   0x01C0 0x0220 
#;
#; Set Length of Ic to be > needed; It will always be truncated
#;   ADDADR   R548 R562 R564
#;   COPYREG  R564 R548
#;   COPYREG  R565 R549
#;
#;**************************************
#;  Temporary Test Code
#    BRANCHNE  R560  17  &TSTP9
tcblock mbipcmd 0x0091 0x03E5   0x01B0 0x0230 0x0011 0x03F9 
#    SETREGS   R518  2   0xD092DL
tcblock mbipcmd 0x0091 0x03E9   0x01B2 0x0206 0x0002 0x092D \
                                0x000D 
#    SETREG    R560  0
tcblock mbipcmd 0x0091 0x03EE   0x0140 0x0230 0x0000 
#    FILLBLK   8:0x00226  0x100000L  32
tcblock mbipcmd 0x0091 0x03F1   0x016C 0x0226 0x4000 0x0000 \
                                0x0010 0x0020 
#    GOTO      &DWNLNK
tcblock mbipcmd 0x0091 0x03F7   0x0156 0x040D 
#TSTP9:
#    BRANCHNE  R561  17  &DWNLNK
tcblock mbipcmd 0x0091 0x03F9   0x01B0 0x0231 0x0011 0x040D 
#    SETREGS   R534  2   0xC00A9L
tcblock mbipcmd 0x0091 0x03FD   0x01B2 0x0216 0x0002 0x00A9 \
                                0x000C 
#    SETREG    R561  0
tcblock mbipcmd 0x0091 0x0402   0x0140 0x0231 0x0000 
#    FILLBLK   9:0x00226  0x100000L  32
tcblock mbipcmd 0x0091 0x0405   0x016C 0x0226 0x4800 0x0000 \
                                0x0010 0x0020 
#    GOTO      &DWNLNK
tcblock mbipcmd 0x0091 0x040B   0x0156 0x040D 
#DWNLNK:
#    NOOP
tcblock mbipcmd 0x0091 0x040D   0x01DE 
#;*************************************
#;   Start Hi-Rate
#    START2HR  0x49  0x4000  0x4800  R518  R534
tcblock mbipcmd 0x0091 0x040E   0x019A 0x0049 0x4000 0x4800 \
                                0x0206 0x0216 
#;
#    SETREG    R143  16
tcblock mbipcmd 0x0091 0x0414   0x0140 0x008F 0x0010 
#    PURGELST  R136                ; Wait 160 ms
tcblock mbipcmd 0x0091 0x0417   0x0190 0x0088 
#    BRANCHNR  0x4000  &EXIT       ; P8 should be busy
tcblock mbipcmd 0x0091 0x0419   0x01A6 0x4000 0x046C 
#;
#    BRANCHGT  R0081   0   &SKIPHR ; BAD > 0; Skip HR
tcblock mbipcmd 0x0091 0x041C   0x01BA 0x0051 0x0000 0x0470 
#    GOTO      &ERREXT             ; Set BAD
tcblock mbipcmd 0x0091 0x0420   0x0156 0x0474 
#;
#;.....................................................
#;
#; Halt Page 8 downlink
#;
#HLTDL8:      
#    BRANCHGT R0081 0  &SKIPHR     ; HR NOK => Skip HR
tcblock mbipcmd 0x0091 0x0422   0x01BA 0x0051 0x0000 0x0470 
#;
#    SETREGS  R552  6  1 0x0000  0x5800  0x00  0xCFFF 0xFF98
tcblock mbipcmd 0x0091 0x0426   0x01B2 0x0228 0x0006 0x0001 \
                                0x0000 0x5800 0x0000 0xCFFF \
                                0xFF98 
#    HRDINIT  R552
tcblock mbipcmd 0x0091 0x042F   0x019C 0x0228 
#    SETREGS  R558  2  0x00000L
tcblock mbipcmd 0x0091 0x0431   0x01B2 0x022E 0x0002 0x0000 \
                                0x0000 
#    START1HR 0x33  0x5800  R558   ; D/L P11 to free P8
tcblock mbipcmd 0x0091 0x0436   0x0174 0x0033 0x5800 0x022E 
#;
#    SETREG   R143  16
tcblock mbipcmd 0x0091 0x043A   0x0140 0x008F 0x0010 
#    PURGELST R136                 ; While away 82 ms
tcblock mbipcmd 0x0091 0x043D   0x0190 0x0088 
#    SETREG   R143  112
tcblock mbipcmd 0x0091 0x043F   0x0140 0x008F 0x0070 
#;
#    BRANCHNR 0x4000 &ERREXT       ; P8 still busy => HR NOK
tcblock mbipcmd 0x0091 0x0442   0x01A6 0x4000 0x0474 
#    GOTO     &VELIMG
tcblock mbipcmd 0x0091 0x0445   0x0156 0x0386 
#;
#;
#; Halt Page 9 downlink
#HLTDL9:      
#    BRANCHEQ R0081 1  &EXIT       ; HR NOK => Skip HR
tcblock mbipcmd 0x0091 0x0447   0x01AE 0x0051 0x0001 0x046C 
#;
#    SETREGS  R552  6  1 0x0000  0x5800  0x00  0xCFFF 0xFF98
tcblock mbipcmd 0x0091 0x044B   0x01B2 0x0228 0x0006 0x0001 \
                                0x0000 0x5800 0x0000 0xCFFF \
                                0xFF98 
#    HRDINIT  R552
tcblock mbipcmd 0x0091 0x0454   0x019C 0x0228 
#    SETREGS  R558  2  0x00000L
tcblock mbipcmd 0x0091 0x0456   0x01B2 0x022E 0x0002 0x0000 \
                                0x0000 
#    START1HR 0x33  0x5800  R558   ; D/L P11 to free P9
tcblock mbipcmd 0x0091 0x045B   0x0174 0x0033 0x5800 0x022E 
#;
#    SETREG   R143  16
tcblock mbipcmd 0x0091 0x045F   0x0140 0x008F 0x0010 
#    PURGELST R136                 ; While away 82 ms
tcblock mbipcmd 0x0091 0x0462   0x0190 0x0088 
#    SETREG   R143  112
tcblock mbipcmd 0x0091 0x0464   0x0140 0x008F 0x0070 
#;
#    BRANCHNR 0x4800 &ERREXT       ; P9 still busy => HR NOK
tcblock mbipcmd 0x0091 0x0467   0x01A6 0x4800 0x0474 
#    GOTO     &Ic1
tcblock mbipcmd 0x0091 0x046A   0x0156 0x03B4 
#;
#;............................................................
#;
#EXIT:
#    SETREG   R0081    0           ; Clear HR NOK Flag
tcblock mbipcmd 0x0091 0x046C   0x0140 0x0051 0x0000 
#    RTNQUE   
tcblock mbipcmd 0x0091 0x046F   0x01FA 
#;
#SKIPHR:
#    ADDREGD  R0081  0xFFFF        ; R81 <- R81 - 1
tcblock mbipcmd 0x0091 0x0470   0x01BC 0x0051 0xFFFF 
#    RTNQUE     
tcblock mbipcmd 0x0091 0x0473   0x01FA 
#;
#ERREXT:
#    SETREG    R0081   3           ; Set HR NOK flag
tcblock mbipcmd 0x0091 0x0474   0x0140 0x0051 0x0003 
#    SETREG    R0026   1           ; Set "Save_Context" Flag
tcblock mbipcmd 0x0091 0x0477   0x0140 0x001A 0x0001 
#    RTNQUE      
tcblock mbipcmd 0x0091 0x047A   0x01FA 
#;
#;--------------------------------------------------------------
#;
#INITREGL:
#;
#    SETREGS   R21  3   0xFFFF  0   0
tcblock mbipcmd 0x0091 0x047B   0x01B2 0x0015 0x0003 0xFFFF \
                                0x0000 0x0000 
#;
#;.....................................
#;
#; Regsiter Usage:
#;
#;     Registers                Usage
#;     168 - 183          Mag Proxy LRDXFR #1
#;     184 - 199                    TWAVG #1
#;     200 - 215                    TWAVG #2
#;     216 - 223                    Copy List to 1
#;     224 - 231                    Copy List to 2
#;
#;     232 - 247          Flux Budget LRDXFR #1
#;     248 - 263                      TWAVG #1
#;     264 - 279                      TWAVG #2
#;     280 - 287                      Copy List to 1
#;     288 - 295                      Copy List to 2
#;
#;     296 - 311          Limb Figure LRDXFR #1
#;     312 - 327                      TWAVG #1
#;     328 - 343                      TWAVG #2
#;     344 - 351                      Copy List to 1
#;     352 - 359                      Copy List to 2
#;
#;--------------------------------------------------------------
#; Register List Assignments:
#;
#;     Register List     Length         Description
#;   1.  R728              24       Weight Table used for MP TWA
#;   2.  R752              24       Weight Table used for FB TWA
#;   3.  R776              24       Weight Table used for LF TWA
#;       
#;      R1024               8       Mag Proxy 1
#;      R1032               8       Mag Proxy 2
#;      R1040               8       Flux Budget 1
#;      R1048               8       Flux Budget 2
#;      R1056               8       Limb Figure 1
#;      R1064               8       Limb Figure 2
#;      R1072               8       Medium-l
#;      R1080               9       Flat fielding fro FB
#;      R1092               8       Bad Pix Correction for Med-l
#;      R1100               9       Flat Field Correction for MP
#;
#;      R1116               5       Copy Vel Table to working area
#;      R1124               5       Copy Recip Table to working ar
#;      R1132               8       Velocity Table
#;      R1140               9       Line Depth Register List
#;
#;      R3040               9       L-Depth Flat Field for Mag Pro
#;      R3052               8       Bad Pixel correction fro Med-l
#;      R3060               9       Continuum Flat Field for FB
#;
#;--------------------------------------------------------------
#; Velocity Register List:
#    SETREGS  $IPRL_STR_VEL60  8  0:0x00514  1:0x00514  5:0x00000 
tcblock mbipcmd 0x0091 0x0481   0x01B2 0x04C7 0x0008 0x0514 \
                                0x0000 0x0514 0x0800 0x0000 \
                                0x2800 0x0002 0x007F 
#    SETREGS  $IPRL_STR_VEL30  8  0:0x00514  1:0x00514  5:0x00000 
tcblock mbipcmd 0x0091 0x048C   0x01B2 0x04CF 0x0008 0x0514 \
                                0x0000 0x0514 0x0800 0x0000 \
                                0x2800 0x0003 0x007F 
#;
#; Line Depth Register List:
#    SETREGS  $IPRL_STR_LD60   9  0:0x00514  1:0x00514  6:0x00000 
tcblock mbipcmd 0x0091 0x0497   0x01B2 0x04E1 0x0009 0x0514 \
                                0x0000 0x0514 0x0800 0x0000 \
                                0x3000 0x0010 0x007F 0x0009 
#    SETREGS  $IPRL_STR_LD30   9  0:0x00514  1:0x00514  6:0x00000 
tcblock mbipcmd 0x0091 0x04A3   0x01B2 0x04EA 0x0009 0x0514 \
                                0x0000 0x0514 0x0800 0x0000 \
                                0x3000 0x0010 0x007F 0x0009 
#;
#; Initalizes Register Sets R168-R231, R232-R295, R296-R359
#;
#; Line Depth
#;
#;   LRDXFR   R168
#;      NpixTotal          0
#;      NpixSeg            0
#;      Seqment            12
#;      Source             17:0xE0000
#;      MaxSource          960
#;      N                  0
#;      K                  0
#;      SegLength          960
#;      DPID               0xBFFFFFB1L
#;      NPixImage          11520L
#;
#;   SETREGS  R168  9  0 0 0 12 17:0xC7C00 960 0 0  ; LRDXFR Regis
#;   SETREGS  R177  5 960 0xBFFF 0xFFB1 11520 0
#;
#; Initialize registers to create two sets of Time Weighted Averag
#    SETREGS  R728  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x04AF   0x01B2 0x02D8 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R736  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x04BA   0x01B2 0x02E0 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R744  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x04C5   0x01B2 0x02E8 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R184  6  7:0x118000   17:0xCA900  17:0xC7C00 
tcblock mbipcmd 0x0091 0x04D0   0x01B2 0x00B8 0x0006 0x8000 \
                                0x3811 0xA900 0x880C 0x7C00 \
                                0x880C 
#    SETREGS  R190  6  0x2D00L  R728  0  24  16
tcblock mbipcmd 0x0091 0x04D9   0x01B2 0x00BE 0x0006 0x2D00 \
                                0x0000 0x02D8 0x0000 0x0018 \
                                0x0010 
#    SETREGS  R200  6  7:0x11C000   17:0xD3000  17:0xC7C00
tcblock mbipcmd 0x0091 0x04E2   0x01B2 0x00C8 0x0006 0xC000 \
                                0x3811 0x3000 0x880D 0x7C00 \
                                0x880C 
#    SETREGS  R206  6  0x2D00L  R728  12  24  16
tcblock mbipcmd 0x0091 0x04EB   0x01B2 0x00CE 0x0006 0x2D00 \
                                0x0000 0x02D8 0x000C 0x0018 \
                                0x0010 
#;
#; Initialize Registers to copy Commanded LF List to working area
#;   SETREGS  R216  6  17:0x11000  17:0x18000  0x1000L
#;   SETREGS  R224  6  17:0x11000  17:0x1F000  0x1000L
#;
#; Continuum Intensity
#;
#;   LRDXFR   R232
#;      NpixTotal          0
#;      NpixSeg            0
#;      Seqment            12
#;      Source             17:0xE2D00
#;      MaxSource          960
#;      N                  0
#;      K                  0
#;      SegLength          960
#;      DPID               0xBFFFFFB1L
#;      NPixImage          11520L
#;
#;   SETREGS  R232  9  0 0 0 12 17:0xD8A00 960 0 0  ; LRDXFR Regis
#;   SETREGS  R241  5 960 0xBFFF 0xFFB2 11520 0
#;
#; Initialize registers to create two sets of Time Weighted Averag
#    SETREGS  R752  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x04F4   0x01B2 0x02F0 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R760  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x04FF   0x01B2 0x02F8 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R768  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x050A   0x01B2 0x0300 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R248  6  6:0x11A000   17:0xDB700  17:0xD8A00 
tcblock mbipcmd 0x0091 0x0515   0x01B2 0x00F8 0x0006 0xA000 \
                                0x3011 0xB700 0x880D 0x8A00 \
                                0x880D 
#    SETREGS  R254  6  0x2D00L  R752  0  24  16
tcblock mbipcmd 0x0091 0x051E   0x01B2 0x00FE 0x0006 0x2D00 \
                                0x0000 0x02F0 0x0000 0x0018 \
                                0x0010 
#    SETREGS  R264  6  6:0x11D000   17:0xE3E00  17:0xD8A00
tcblock mbipcmd 0x0091 0x0527   0x01B2 0x0108 0x0006 0xD000 \
                                0x3011 0x3E00 0x880E 0x8A00 \
                                0x880D 
#    SETREGS  R270  6  0x2D00L  R752  12  24  16
tcblock mbipcmd 0x0091 0x0530   0x01B2 0x010E 0x0006 0x2D00 \
                                0x0000 0x02F0 0x000C 0x0018 \
                                0x0010 
#;
#; Initialize Registers to copy Commanded LF List to working area
#;   SETREGS  R280  6  17:0x21000  17:0x28000  0x1000L
#;   SETREGS  R288  6  17:0x21000  17:0x16000  0x1000L
#;
#; Limb Figure 
#;
#;   LRDXFR   R296
#;      NpixTotal          0
#;      NpixSeg            0
#;      Seqment            12
#;      Source             17:0xE5A00
#;      MaxSource          1280
#;      N                  0
#;      K                  0
#;      SegLength          1280
#;      DPID               0xBFFFFFB1L
#;      NPixImage          15360L
#;
#;   SETREGS  R296  9  0 0 0 12 17:0xE9800 1280 0 0  ; LRDXFR Regi
#;   SETREGS  R305  5 1280 0xBFFF 0xFFB3 15360 16
#;
#;
#; Initialize registers to create two sets of Time Weighted Averag
#    SETREGS  R776  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x0539   0x01B2 0x0308 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R784  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x0544   0x01B2 0x0310 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R792  8  1  1  1  1  1  1  1  1
tcblock mbipcmd 0x0091 0x054F   0x01B2 0x0318 0x0008 0x0001 \
                                0x0001 0x0001 0x0001 0x0001 \
                                0x0001 0x0001 0x0001 
#    SETREGS  R312  6  6:0x110000   17:0xED400  17:0xE9800 
tcblock mbipcmd 0x0091 0x055A   0x01B2 0x0138 0x0006 0x0000 \
                                0x3011 0xD400 0x880E 0x9800 \
                                0x880E 
#    SETREGS  R318  6  0x3C00L  R776  0  24  16
tcblock mbipcmd 0x0091 0x0563   0x01B2 0x013E 0x0006 0x3C00 \
                                0x0000 0x0308 0x0000 0x0018 \
                                0x0010 
#    SETREGS  R328  6  6:0x115000   17:0xF8000  17:0xE9800
tcblock mbipcmd 0x0091 0x056C   0x01B2 0x0148 0x0006 0x5000 \
                                0x3011 0x8000 0x880F 0x9800 \
                                0x880E 
#    SETREGS  R334  6  0x3C00L  R776  12  24 16
tcblock mbipcmd 0x0091 0x0575   0x01B2 0x014E 0x0006 0x3C00 \
                                0x0000 0x0308 0x000C 0x0018 \
                                0x0010 
#;
#; Initialize Registers to copy Commanded LF List to working area
#    SETREGS  R344  6  17:0x01000  17:0x03000  0x2000L
tcblock mbipcmd 0x0091 0x057E   0x01B2 0x0158 0x0006 0x1000 \
                                0x8800 0x3000 0x8800 0x2000 \
                                0x0000 
#    SETREGS  R352  6  17:0x01000  17:0x05000  0x2000L
tcblock mbipcmd 0x0091 0x0587   0x01B2 0x0160 0x0006 0x1000 \
                                0x8800 0x5000 0x8800 0x2000 \
                                0x0000 
#;
#; Set initial operating parameters
#;   _COPYLST R216                  ;MP RWBIN 1 <-- New MP RWBIN
#;   _COPYLST R224                  ;MP RWBIN 2 <-- New MP RWBIN
#;   _COPYLST R280                  ;FB RWBIN 1 <-- New FB RWBIN
#;   _COPYLST R288                  ;FB RWBIN 2 <-- New FB RWBIN
#    _COPYLST R344                  ; LFCropList1 <- New LF Crop L
tcblock mbipcmd 0x0091 0x0590   0x81C2 0x0158 
#    _COPYLST R352                  ; LFCropList1 <- New LF Crop L
tcblock mbipcmd 0x0091 0x0592   0x81C2 0x0160 
#;
#    COPYRD2D R168  R374  14   ; L-Depth initial Value Reg Bank ->
tcblock mbipcmd 0x0091 0x0594   0x0144 0x00A8 0x0176 0x000E 
#    COPYRD2D R232  R388  14   ; Continuum Intensity register set
tcblock mbipcmd 0x0091 0x0598   0x0144 0x00E8 0x0184 0x000E 
#    COPYRD2D R296  R402  14   ; Set LRDXFR from set 1
tcblock mbipcmd 0x0091 0x059C   0x0144 0x0128 0x0192 0x000E 
#;
#    COPYRD2D R184  R908  12        ; Reset MP TWA parameter set #
tcblock mbipcmd 0x0091 0x05A0   0x0144 0x00B8 0x038C 0x000C 
#    COPYRD2D R200  R928  12        ; Reset MP TWA parameter set #
tcblock mbipcmd 0x0091 0x05A4   0x0144 0x00C8 0x03A0 0x000C 
#    COPYRD2D R248  R960  12        ; Reset FB TWA parameter set #
tcblock mbipcmd 0x0091 0x05A8   0x0144 0x00F8 0x03C0 0x000C 
#    COPYRD2D R264  R980  12        ; Reset FB TWA parameter set #
tcblock mbipcmd 0x0091 0x05AC   0x0144 0x0108 0x03D4 0x000C 
#    COPYRD2D R312  R864  12        ; Reset LF TWA parameter set #
tcblock mbipcmd 0x0091 0x05B0   0x0144 0x0138 0x0360 0x000C 
#    COPYRD2D R328  R888  12        ; Reset LF TWA parameter set #
tcblock mbipcmd 0x0091 0x05B4   0x0144 0x0148 0x0378 0x000C 
#;
#; Initialize Register Lists 
#;
#; Magnetic Proxy
#    SETREGS    R1024  8  0x0800   7:0x118000  0 0x0008  17:0x1100
tcblock mbipcmd 0x0091 0x05B8   0x01B2 0x0400 0x0008 0x0800 \
                                0x8000 0x3811 0x0000 0x0008 \
                                0x1000 0x8801 0x0045 
#    SETREGS    R1032  8  0x0800   7:0x11C000  0 0x0008  17:0x1100
tcblock mbipcmd 0x0091 0x05C3   0x01B2 0x0408 0x0008 0x0800 \
                                0xC000 0x3811 0x0000 0x0008 \
                                0x1000 0x8801 0x0045 
#    SETREGS    R3040  9 6:0x00000 10:0x20000  1:0x00000  0x100000
tcblock mbipcmd 0x0091 0x05CE   0x01B2 0x0BE0 0x0009 0x0000 \
                                0x3000 0x0000 0x5002 0x0000 \
                                0x0800 0x0000 0x0010 0x0010 
#;
#; Flux Budget
#    SETREGS    R1040  8  0x0800   6:0x11A000  0 0x0008  17:0x2100
tcblock mbipcmd 0x0091 0x05DA   0x01B2 0x0410 0x0008 0x0800 \
                                0xA000 0x3011 0x0000 0x0008 \
                                0x1000 0x8802 0x0045 
#    SETREGS    R1048  8  0x0800   6:0x11D000  0 0x0008  17:0x2100
tcblock mbipcmd 0x0091 0x05E5   0x01B2 0x0418 0x0008 0x0800 \
                                0xD000 0x3011 0x0000 0x0008 \
                                0x1000 0x8802 0x0045 
#    SETREGS    R3060  9 7:0x00000 10:0x20000  1:0x00000  0x100000
tcblock mbipcmd 0x0091 0x05F0   0x01B2 0x0BF4 0x0009 0x0000 \
                                0x3800 0x0000 0x5002 0x0000 \
                                0x0800 0x0000 0x0010 0x0010 
#;
#; Limb Figure
#;   SETREGS    R1056  8  0x5800   6:0x110000  0   2000  17:0x0300
#    SETREGS    R1056  8  0x3800   6:0x110000  0   2000  17:0x0300
tcblock mbipcmd 0x0091 0x05FC   0x01B2 0x0420 0x0008 0x3800 \
                                0x0000 0x3011 0x0000 0x07D0 \
                                0x3000 0x8800 0x0045 
#;   SETREGS    R1064  8  0x5000   6:0x115000  0   2000  17:0x0500
#    SETREGS    R1064  8  0x3800   6:0x115000  0   2000  17:0x0500
tcblock mbipcmd 0x0091 0x0607   0x01B2 0x0428 0x0008 0x3800 \
                                0x5000 0x3011 0x0000 0x07D0 \
                                0x5000 0x8800 0x0045 
#;
#; Medium-l
#;   SETREGS    R1072  8  0x2800   7:0x110000  0 0x0006  17:0x0700
#    SETREGS    R1072  8  0x0800   7:0x110000  0 0x0006  17:0x0700
tcblock mbipcmd 0x0091 0x0612   0x01B2 0x0430 0x0008 0x0800 \
                                0x0000 0x3811 0x0000 0x0006 \
                                0x7000 0x8800 0x0045 
#    SETREGS    R3052  8 5:0x00000 10:0x20000  1:0x00000  0x100000
tcblock mbipcmd 0x0091 0x061D   0x01B2 0x0BEC 0x0008 0x0000 \
                                0x2800 0x0000 0x5002 0x0000 \
                                0x0800 0x0000 0x0010 
#;
#;
#; Register lists for copying Reciprocal and Velocity 
#; tables to working area
#    SETREGS   R1116 5  0x0000  0x000B  0x8000  0x800A  4
tcblock mbipcmd 0x0091 0x0628   0x01B2 0x045C 0x0005 0x0000 \
                                0x000B 0x8000 0x800A 0x0004 
#    SETREGS   R1124 5  0x8000  0x0009  0x0000  0x800A  4
tcblock mbipcmd 0x0091 0x0630   0x01B2 0x0464 0x0005 0x8000 \
                                0x0009 0x0000 0x800A 0x0004 
#; 
#; Register List for Error log dump
#    SETREGS   R460  9 0 0 0 1 4:0x110000 4800 0 0
tcblock mbipcmd 0x0091 0x0638   0x01B2 0x01CC 0x0009 0x0000 \
                                0x0000 0x0000 0x0001 0x0000 \
                                0x2011 0x12C0 0x0000 0x0000 
#    SETREGS   R469  5 4800 0xBFFF 0xFFED 4800 0
tcblock mbipcmd 0x0091 0x0644   0x01B2 0x01D5 0x0005 0x12C0 \
                                0xBFFF 0xFFED 0x12C0 0x0000 
#;
#    SETREGS    R562   2  0x20000L
tcblock mbipcmd 0x0091 0x064C   0x01B2 0x0232 0x0002 0x0000 \
                                0x0002 
#;
#    RTNQUE
tcblock mbipcmd 0x0091 0x0651   0x01FA 
#;
#;
#;
#;................................................................
#;
#;
#;  5k Data:
#;    Medium-l    80%   15360
#;    Limb Figure  5%     960     (Time Wtd. Avg)
#;    Line Depth   5%     960     (  "   "    " )
#;    Continuum    5%     960     (  "   "    " )
#;    LOI-V       2.5%    480
#;    LOI-C       2.5%    480
#;
#;
#;  Map of List Memory:
#;
#;   Address Range                 Description
#;     17:0x000000            Full Disk Crop List
#;     17:0x001000            Limb Figure Crop List
#;     17:0x003000            LF List #1
#;     17:0x005000            LF List #2
#;     17:0x007000            Vector Weighted Bin List (Med-l)
#;     17:0x011000            Rectangular Weighted Bin List (Mag P
#;     17:0x021000            RWBin List (Flux Budget)
#;
#;     17:0x0C7C00            Line Depth Output Buffer #1
#;     17:0x0CA900            Line Depth Accumulation Buffer #1
#;     17:0x0D0300            Line Depth Output Buffer #2
#;     17:0x0D3000            Line Depth Accumulation Buffer #2
#;     17:0x0D8A00            Continuum Intensity Output Buffer #1
#;     17:0x0DB700            Continuum Intensity Acc. Buffer #1
#;     17:0x0E1100            Continuum Intensity Output Buffer #2
#;     17:0x0E3E00            Continuum Intensity Acc. Buffer #2
#;     17:0x0E9800            Limb Figure Output Buffer #1
#;     17:0x0ED400            Limb Figure Acc. Buffer #1
#;     17:0x0F4C00            Limb Figure Output Buffer #2
#;     17:0x0F8800            Limb Figure Acc. Buffer #2
#;
#; 2 Mar 95: Use a single output buffer for TWA DP.'s.
#; 6 Mar 95: Reassigned Register banks to eliminate 2nd LRDXFR
#;           Assigned List copying registers to start at 
#;           4 Register boundry.
#;...........................................................
#;
#INITDATA:
#;
#;   
#; Initilization
#;
#    FILLBLK  7:0x110000  15360L  0xA123    ; Med-l  data block
tcblock mbipcmd 0x0091 0x0652   0x016C 0x0000 0x3811 0x3C00 \
                                0x0000 0xA123 
#    FILLBLK  7:0x113C00    960L  0xB456
tcblock mbipcmd 0x0091 0x0658   0x016C 0x3C00 0x3811 0x03C0 \
                                0x0000 0xB456 
#    FILLBLK  7:0x113FC0    960L  0xC789
tcblock mbipcmd 0x0091 0x065E   0x016C 0x3FC0 0x3811 0x03C0 \
                                0x0000 0xC789 
#    FILLBLK  7:0x114380    960L  0x0D23
tcblock mbipcmd 0x0091 0x0664   0x016C 0x4380 0x3811 0x03C0 \
                                0x0000 0x0D23 
#    FILLBLK  7:0x114740    480L  0x0E45
tcblock mbipcmd 0x0091 0x066A   0x016C 0x4740 0x3811 0x01E0 \
                                0x0000 0x0E45 
#    FILLBLK  7:0x114920    480L  0x0F67
tcblock mbipcmd 0x0091 0x0670   0x016C 0x4920 0x3811 0x01E0 \
                                0x0000 0x0F67 
#    FILLBLK 13:0x000000 0x100000L 0x0001
tcblock mbipcmd 0x0091 0x0676   0x016C 0x0000 0x6800 0x0000 \
                                0x0010 0x0001 
#    SETREGS  R1016 6  13:0x000000  10:0x000000  0x100000L
tcblock mbipcmd 0x0091 0x067C   0x01B2 0x03F8 0x0006 0x0000 \
                                0x6800 0x0000 0x5000 0x0000 \
                                0x0010 
#    DAT2LST  R1016
tcblock mbipcmd 0x0091 0x0685   0x01C4 0x03F8 
#;
#;
#; The accumulation and output buffers for Time Weighted Averages 
#; in a List memory Page (8 byte EDAC). 
#;
#; Line Depth Telemetry buffer
#    FILLBLK 17:0xC7C00    960L  0x3300 
tcblock mbipcmd 0x0091 0x0687   0x016C 0x7C00 0x880C 0x03C0 \
                                0x0000 0x3300 
#    FILLBLK 17:0xC7FC0    960L  0x3310
tcblock mbipcmd 0x0091 0x068D   0x016C 0x7FC0 0x880C 0x03C0 \
                                0x0000 0x3310 
#    FILLBLK 17:0xC8380    960L  0x3320
tcblock mbipcmd 0x0091 0x0693   0x016C 0x8380 0x880C 0x03C0 \
                                0x0000 0x3320 
#    FILLBLK 17:0xC8740    960L  0x3330
tcblock mbipcmd 0x0091 0x0699   0x016C 0x8740 0x880C 0x03C0 \
                                0x0000 0x3330 
#    FILLBLK 17:0xC8B00    960L  0x3340
tcblock mbipcmd 0x0091 0x069F   0x016C 0x8B00 0x880C 0x03C0 \
                                0x0000 0x3340 
#    FILLBLK 17:0xC8EC0    960L  0x3350
tcblock mbipcmd 0x0091 0x06A5   0x016C 0x8EC0 0x880C 0x03C0 \
                                0x0000 0x3350 
#    FILLBLK 17:0xC9280    960L  0x3360
tcblock mbipcmd 0x0091 0x06AB   0x016C 0x9280 0x880C 0x03C0 \
                                0x0000 0x3360 
#    FILLBLK 17:0xC9640    960L  0x3370
tcblock mbipcmd 0x0091 0x06B1   0x016C 0x9640 0x880C 0x03C0 \
                                0x0000 0x3370 
#    FILLBLK 17:0xC9A00    960L  0x3380
tcblock mbipcmd 0x0091 0x06B7   0x016C 0x9A00 0x880C 0x03C0 \
                                0x0000 0x3380 
#    FILLBLK 17:0xC9DC0    960L  0x3390
tcblock mbipcmd 0x0091 0x06BD   0x016C 0x9DC0 0x880C 0x03C0 \
                                0x0000 0x3390 
#    FILLBLK 17:0xCA180    960L  0x33A0
tcblock mbipcmd 0x0091 0x06C3   0x016C 0xA180 0x880C 0x03C0 \
                                0x0000 0x33A0 
#    FILLBLK 17:0xCA540    960L  0x33B0
tcblock mbipcmd 0x0091 0x06C9   0x016C 0xA540 0x880C 0x03C0 \
                                0x0000 0x33B0 
#;
#    FILLBLK 17:0xD0300    960L  0x3301
tcblock mbipcmd 0x0091 0x06CF   0x016C 0x0300 0x880D 0x03C0 \
                                0x0000 0x3301 
#    FILLBLK 17:0xD06C0    960L  0x3311
tcblock mbipcmd 0x0091 0x06D5   0x016C 0x06C0 0x880D 0x03C0 \
                                0x0000 0x3311 
#    FILLBLK 17:0xD0A80    960L  0x3321
tcblock mbipcmd 0x0091 0x06DB   0x016C 0x0A80 0x880D 0x03C0 \
                                0x0000 0x3321 
#    FILLBLK 17:0xD0E40    960L  0x3331
tcblock mbipcmd 0x0091 0x06E1   0x016C 0x0E40 0x880D 0x03C0 \
                                0x0000 0x3331 
#    FILLBLK 17:0xD1200    960L  0x3341
tcblock mbipcmd 0x0091 0x06E7   0x016C 0x1200 0x880D 0x03C0 \
                                0x0000 0x3341 
#    FILLBLK 17:0xD15C0    960L  0x3351
tcblock mbipcmd 0x0091 0x06ED   0x016C 0x15C0 0x880D 0x03C0 \
                                0x0000 0x3351 
#    FILLBLK 17:0xD1980    960L  0x3361
tcblock mbipcmd 0x0091 0x06F3   0x016C 0x1980 0x880D 0x03C0 \
                                0x0000 0x3361 
#    FILLBLK 17:0xD1D40    960L  0x3371
tcblock mbipcmd 0x0091 0x06F9   0x016C 0x1D40 0x880D 0x03C0 \
                                0x0000 0x3371 
#    FILLBLK 17:0xD2100    960L  0x3381
tcblock mbipcmd 0x0091 0x06FF   0x016C 0x2100 0x880D 0x03C0 \
                                0x0000 0x3381 
#    FILLBLK 17:0xD24C0    960L  0x3391
tcblock mbipcmd 0x0091 0x0705   0x016C 0x24C0 0x880D 0x03C0 \
                                0x0000 0x3391 
#    FILLBLK 17:0xD2880    960L  0x33A1
tcblock mbipcmd 0x0091 0x070B   0x016C 0x2880 0x880D 0x03C0 \
                                0x0000 0x33A1 
#    FILLBLK 17:0xD2C40    960L  0x33B1
tcblock mbipcmd 0x0091 0x0711   0x016C 0x2C40 0x880D 0x03C0 \
                                0x0000 0x33B1 
#;
#; Continuum Intensity Telemetry Buffer
#    FILLBLK 17:0xD8A00    960L  0x4400
tcblock mbipcmd 0x0091 0x0717   0x016C 0x8A00 0x880D 0x03C0 \
                                0x0000 0x4400 
#    FILLBLK 17:0xD8DC0    960L  0x4410
tcblock mbipcmd 0x0091 0x071D   0x016C 0x8DC0 0x880D 0x03C0 \
                                0x0000 0x4410 
#    FILLBLK 17:0xD9180    960L  0x4420
tcblock mbipcmd 0x0091 0x0723   0x016C 0x9180 0x880D 0x03C0 \
                                0x0000 0x4420 
#    FILLBLK 17:0xD9540    960L  0x4430
tcblock mbipcmd 0x0091 0x0729   0x016C 0x9540 0x880D 0x03C0 \
                                0x0000 0x4430 
#    FILLBLK 17:0xD9900    960L  0x4440
tcblock mbipcmd 0x0091 0x072F   0x016C 0x9900 0x880D 0x03C0 \
                                0x0000 0x4440 
#    FILLBLK 17:0xD9CC0    960L  0x4450
tcblock mbipcmd 0x0091 0x0735   0x016C 0x9CC0 0x880D 0x03C0 \
                                0x0000 0x4450 
#    FILLBLK 17:0xDA080    960L  0x4460
tcblock mbipcmd 0x0091 0x073B   0x016C 0xA080 0x880D 0x03C0 \
                                0x0000 0x4460 
#    FILLBLK 17:0xDA440    960L  0x4470
tcblock mbipcmd 0x0091 0x0741   0x016C 0xA440 0x880D 0x03C0 \
                                0x0000 0x4470 
#    FILLBLK 17:0xDA800    960L  0x4480
tcblock mbipcmd 0x0091 0x0747   0x016C 0xA800 0x880D 0x03C0 \
                                0x0000 0x4480 
#    FILLBLK 17:0xDABC0    960L  0x4490
tcblock mbipcmd 0x0091 0x074D   0x016C 0xABC0 0x880D 0x03C0 \
                                0x0000 0x4490 
#    FILLBLK 17:0xDAF80    960L  0x44A0
tcblock mbipcmd 0x0091 0x0753   0x016C 0xAF80 0x880D 0x03C0 \
                                0x0000 0x44A0 
#    FILLBLK 17:0xDB340    960L  0x44B0
tcblock mbipcmd 0x0091 0x0759   0x016C 0xB340 0x880D 0x03C0 \
                                0x0000 0x44B0 
#;
#    FILLBLK 17:0xE1100    960L  0x4401
tcblock mbipcmd 0x0091 0x075F   0x016C 0x1100 0x880E 0x03C0 \
                                0x0000 0x4401 
#    FILLBLK 17:0xE14C0    960L  0x4411
tcblock mbipcmd 0x0091 0x0765   0x016C 0x14C0 0x880E 0x03C0 \
                                0x0000 0x4411 
#    FILLBLK 17:0xE1880    960L  0x4421
tcblock mbipcmd 0x0091 0x076B   0x016C 0x1880 0x880E 0x03C0 \
                                0x0000 0x4421 
#    FILLBLK 17:0xE1C40    960L  0x4431
tcblock mbipcmd 0x0091 0x0771   0x016C 0x1C40 0x880E 0x03C0 \
                                0x0000 0x4431 
#    FILLBLK 17:0xE2000    960L  0x4441
tcblock mbipcmd 0x0091 0x0777   0x016C 0x2000 0x880E 0x03C0 \
                                0x0000 0x4441 
#    FILLBLK 17:0xE23C0    960L  0x4451
tcblock mbipcmd 0x0091 0x077D   0x016C 0x23C0 0x880E 0x03C0 \
                                0x0000 0x4451 
#    FILLBLK 17:0xE2780    960L  0x4461
tcblock mbipcmd 0x0091 0x0783   0x016C 0x2780 0x880E 0x03C0 \
                                0x0000 0x4461 
#    FILLBLK 17:0xE2B40    960L  0x4471
tcblock mbipcmd 0x0091 0x0789   0x016C 0x2B40 0x880E 0x03C0 \
                                0x0000 0x4471 
#    FILLBLK 17:0xE2F00    960L  0x4481
tcblock mbipcmd 0x0091 0x078F   0x016C 0x2F00 0x880E 0x03C0 \
                                0x0000 0x4481 
#    FILLBLK 17:0xE32C0    960L  0x4491
tcblock mbipcmd 0x0091 0x0795   0x016C 0x32C0 0x880E 0x03C0 \
                                0x0000 0x4491 
#    FILLBLK 17:0xE3680    960L  0x44A1
tcblock mbipcmd 0x0091 0x079B   0x016C 0x3680 0x880E 0x03C0 \
                                0x0000 0x44A1 
#    FILLBLK 17:0xE3A40    960L  0x44B1
tcblock mbipcmd 0x0091 0x07A1   0x016C 0x3A40 0x880E 0x03C0 \
                                0x0000 0x44B1 
#;
#; Limb Figure Telemetry Buffer  #1
#    FILLBLK 17:0xE9800    1280L  0x5500
tcblock mbipcmd 0x0091 0x07A7   0x016C 0x9800 0x880E 0x0500 \
                                0x0000 0x5500 
#    FILLBLK 17:0xE9D00    1280L  0x5510
tcblock mbipcmd 0x0091 0x07AD   0x016C 0x9D00 0x880E 0x0500 \
                                0x0000 0x5510 
#    FILLBLK 17:0xEA200    1280L  0x5520
tcblock mbipcmd 0x0091 0x07B3   0x016C 0xA200 0x880E 0x0500 \
                                0x0000 0x5520 
#    FILLBLK 17:0xEA700    1280L  0x5530
tcblock mbipcmd 0x0091 0x07B9   0x016C 0xA700 0x880E 0x0500 \
                                0x0000 0x5530 
#    FILLBLK 17:0xEAC00    1280L  0x5540
tcblock mbipcmd 0x0091 0x07BF   0x016C 0xAC00 0x880E 0x0500 \
                                0x0000 0x5540 
#    FILLBLK 17:0xEB100    1280L  0x5550
tcblock mbipcmd 0x0091 0x07C5   0x016C 0xB100 0x880E 0x0500 \
                                0x0000 0x5550 
#    FILLBLK 17:0xEB600    1280L  0x5560
tcblock mbipcmd 0x0091 0x07CB   0x016C 0xB600 0x880E 0x0500 \
                                0x0000 0x5560 
#    FILLBLK 17:0xEBB00    1280L  0x5570
tcblock mbipcmd 0x0091 0x07D1   0x016C 0xBB00 0x880E 0x0500 \
                                0x0000 0x5570 
#    FILLBLK 17:0xEC000    1280L  0x5580
tcblock mbipcmd 0x0091 0x07D7   0x016C 0xC000 0x880E 0x0500 \
                                0x0000 0x5580 
#    FILLBLK 17:0xEC500    1280L  0x5590
tcblock mbipcmd 0x0091 0x07DD   0x016C 0xC500 0x880E 0x0500 \
                                0x0000 0x5590 
#    FILLBLK 17:0xECA00    1280L  0x55A0
tcblock mbipcmd 0x0091 0x07E3   0x016C 0xCA00 0x880E 0x0500 \
                                0x0000 0x55A0 
#    FILLBLK 17:0xECF00    1280L  0x55B0
tcblock mbipcmd 0x0091 0x07E9   0x016C 0xCF00 0x880E 0x0500 \
                                0x0000 0x55B0 
#;
#; Limb Figure Telemetry Buffer  #2
#    FILLBLK 17:0xF4C00    1280L  0x6601
tcblock mbipcmd 0x0091 0x07EF   0x016C 0x4C00 0x880F 0x0500 \
                                0x0000 0x6601 
#    FILLBLK 17:0xF5100    1280L  0x6611
tcblock mbipcmd 0x0091 0x07F5   0x016C 0x5100 0x880F 0x0500 \
                                0x0000 0x6611 
#    FILLBLK 17:0xF5600    1280L  0x6621
tcblock mbipcmd 0x0091 0x07FB   0x016C 0x5600 0x880F 0x0500 \
                                0x0000 0x6621 
#    FILLBLK 17:0xF5B00    1280L  0x6631
tcblock mbipcmd 0x0091 0x0801   0x016C 0x5B00 0x880F 0x0500 \
                                0x0000 0x6631 
#    FILLBLK 17:0xF6000    1280L  0x6641
tcblock mbipcmd 0x0091 0x0807   0x016C 0x6000 0x880F 0x0500 \
                                0x0000 0x6641 
#    FILLBLK 17:0xF6500    1280L  0x6651
tcblock mbipcmd 0x0091 0x080D   0x016C 0x6500 0x880F 0x0500 \
                                0x0000 0x6651 
#    FILLBLK 17:0xF6A00    1280L  0x6661
tcblock mbipcmd 0x0091 0x0813   0x016C 0x6A00 0x880F 0x0500 \
                                0x0000 0x6661 
#    FILLBLK 17:0xF6F00    1280L  0x6671
tcblock mbipcmd 0x0091 0x0819   0x016C 0x6F00 0x880F 0x0500 \
                                0x0000 0x6671 
#    FILLBLK 17:0xF7400    1280L  0x6681
tcblock mbipcmd 0x0091 0x081F   0x016C 0x7400 0x880F 0x0500 \
                                0x0000 0x6681 
#    FILLBLK 17:0xF7900    1280L  0x6691
tcblock mbipcmd 0x0091 0x0825   0x016C 0x7900 0x880F 0x0500 \
                                0x0000 0x6691 
#    FILLBLK 17:0xF7E00    1280L  0x66A1
tcblock mbipcmd 0x0091 0x082B   0x016C 0x7E00 0x880F 0x0500 \
                                0x0000 0x66A1 
#    FILLBLK 17:0xF8300    1280L  0x66B1
tcblock mbipcmd 0x0091 0x0831   0x016C 0x8300 0x880F 0x0500 \
                                0x0000 0x66B1 
#;
#; Clear TWA Accumulation Buffers
#    FILLBLK  0:0x00000    0x100000L  0     ; P0 <= 0
tcblock mbipcmd 0x0091 0x0837   0x016C 0x0000 0x0000 0x0000 \
                                0x0010 0x0000 
#    SETREGS  R500  6  0:0x00000  17:0xC7C00  0x38400L  ; P0 -> P1
tcblock mbipcmd 0x0091 0x083D   0x01B2 0x01F4 0x0006 0x0000 \
                                0x0000 0x7C00 0x880C 0x8400 \
                                0x0003 
#    DAT2LST  R500
tcblock mbipcmd 0x0091 0x0846   0x01C4 0x01F4 
#;
#    RTNQUE
tcblock mbipcmd 0x0091 0x0848   0x01FA 
#;
#;   GOTO  &INITREGL
#;   END
#;
#;============================================================
#=======================================================
#
# ENBQUE                ; Enable Queue
tcblock mbipldin 0x0136
#
#
return
#
#=======================================================
