# File: cam_reg6_v01.src
#
program "%Z% MODULE: %M% RELEASE: %R%.%L% CREATED: %G% %U%"
source "/mdisw/cfl/flight/src/cam_reg6_v01.src"
descr "Loads IP queue instructions"
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  1-Mar-1996 17:08:59.00
#; Input File: cam_reg6_v01.reg
#;
#;
#;IPRL_SUMDIFF_PARAM
#SETREGS R5024  10 0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13A0 0x000A 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_SUMDIFF_WORK
#SETREGS R5034  11 0:0x0  0:0x0  0:0x0  0x100000L  1  1  16
tcblock mbipldin    0x01B2 0x13AA 0x000B 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0010 0x0001 0x0001 0x0010 
#;
#;IPRL_SQRT_PARAM
#SETREGS R5045   8 0:0x0  0:0x0  0x100000L  0  9
tcblock mbipldin    0x01B2 0x13B5 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0010 0x0000 \
                    0x0009 
#;
#;IPRL_SQRT_OLDHEAD
#SETREGS R5053  10 0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13BD 0x000A 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_FLTGRAM_SD
#SETREGS R5063   3 0xe5  0x0009  0x2000
tcblock mbipldin    0x01B2 0x13C7 0x0003 0x00E5 0x0009 \
                    0x2000 
#;
#;IPRL_FLTGRAM_SI
#SETREGS R5066   3 0xe5  0x000a  0x2000
tcblock mbipldin    0x01B2 0x13CA 0x0003 0x00E5 0x000A \
                    0x2000 
#;
#;IPRL_LDEP_PARAM
#SETREGS R5069  12 0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13CD 0x000C 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_CONT_PARAM
#SETREGS R5081  13 0  0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13D9 0x000D 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 
#;
#;IPRL_CONT_WORK
#SETREGS R5094  10 17:0x0726  0  0  18:0x0726  0  0  0  0
tcblock mbipldin    0x01B2 0x13E6 0x000A 0x0726 0x8800 \
                    0x0000 0x0000 0x0726 0x9000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_EXTRACT_80K
#SETREGS R5104   6 0x0c8000L  1024  800  1024  0x2e00
tcblock mbipldin    0x01B2 0x13F0 0x0006 0x8000 0x000C \
                    0x0400 0x0320 0x0400 0x2E00 
#;
#;IPRL_EXTRACT_300
#SETREGS R5110   6 0x15f90L  1024  300  300  0x2f00
tcblock mbipldin    0x01B2 0x13F6 0x0006 0x5F90 0x0001 \
                    0x0400 0x012C 0x012C 0x2F00 
#;
#;IPRL_EXTRACT_350
#SETREGS R5116   6 0x1de84L  1024  350  350  0x2f01
tcblock mbipldin    0x01B2 0x13FC 0x0006 0xDE84 0x0001 \
                    0x0400 0x015E 0x015E 0x2F01 
#;
#;IPRL_EXTRACT_400
#SETREGS R5122   6 0x27100L  1024  400  400  0x2f02
tcblock mbipldin    0x01B2 0x1402 0x0006 0x7100 0x0002 \
                    0x0400 0x0190 0x0190 0x2F02 
#;
#;IPRL_EXTRACT_450
#SETREGS R5128   6 0x31704L  1024  450  450  0x2f03
tcblock mbipldin    0x01B2 0x1408 0x0006 0x1704 0x0003 \
                    0x0400 0x01C2 0x01C2 0x2F03 
#;
#;IPRL_EXTRACT_550
#SETREGS R5134   6 0x49da4L  1024  550  550  0x2f04
tcblock mbipldin    0x01B2 0x140E 0x0006 0x9DA4 0x0004 \
                    0x0400 0x0226 0x0226 0x2F04 
#=======================================================
#
return
#
#=======================================================
