# File: /mdisw/cfl/flight/src/baseload_camreg_bck_v01.src
#
program "%Z% MODULE: %M% RELEASE: %R%.%L% CREATED: %G% %U%"
#=======================================================
source "/mdisw/cfl/flight/src/baseload_camreg_bck_v01.src"
descr "Load of MDI IP campaign registers"
#
#
#=======================================================
#
# File: cam_reg_v03.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 12-Dec-1995 22:09:18.00
#; Input File: cam_reg_v03.tab
#;
#;
#;IPRP_HDECODE_PAGE0
#SETREGS R4096  10 0:0x0226  0x6800  0  0  1  0  0  0  0
tcblock mbipldin    0x01B2 0x1000 0x000A 0x0226 0x0000 \
                    0x6800 0x0000 0x0000 0x0001 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE1
#SETREGS R4106  10 1:0x0226  0x6800  0  0  2  0  0  0  0
tcblock mbipldin    0x01B2 0x100A 0x000A 0x0226 0x0800 \
                    0x6800 0x0000 0x0000 0x0002 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE2
#SETREGS R4116  10 2:0x0226  0x6800  0  0  3  0  0  0  0
tcblock mbipldin    0x01B2 0x1014 0x000A 0x0226 0x1000 \
                    0x6800 0x0000 0x0000 0x0003 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE3
#SETREGS R4126  10 3:0x0226  0x6800  0  0  4  0  0  0  0
tcblock mbipldin    0x01B2 0x101E 0x000A 0x0226 0x1800 \
                    0x6800 0x0000 0x0000 0x0004 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE4
#SETREGS R4136  10 4:0x0726  0x6800  0  0  5  0  0  0  0
tcblock mbipldin    0x01B2 0x1028 0x000A 0x0726 0x2000 \
                    0x6800 0x0000 0x0000 0x0005 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE5
#SETREGS R4146  10 5:0x0726  0x6800  0  0  6  0  0  0  0
tcblock mbipldin    0x01B2 0x1032 0x000A 0x0726 0x2800 \
                    0x6800 0x0000 0x0000 0x0006 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE6
#SETREGS R4156  10 6:0x0726  0x6800  0  0  7  0  0  0  0
tcblock mbipldin    0x01B2 0x103C 0x000A 0x0726 0x3000 \
                    0x6800 0x0000 0x0000 0x0007 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE7
#SETREGS R4166  10 7:0x0726  0x6800  0  0  8  0  0  0  0
tcblock mbipldin    0x01B2 0x1046 0x000A 0x0726 0x3800 \
                    0x6800 0x0000 0x0000 0x0008 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE8
#SETREGS R4176  10 8:0x0226  0x6800  0  0  8  0  0  0  0
tcblock mbipldin    0x01B2 0x1050 0x000A 0x0226 0x4000 \
                    0x6800 0x0000 0x0000 0x0008 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE9
#SETREGS R4186  10 9:0x0226  0x6800  0  0  8  0  0  0  0
tcblock mbipldin    0x01B2 0x105A 0x000A 0x0226 0x4800 \
                    0x6800 0x0000 0x0000 0x0008 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE10
#SETREGS R4196  10 10:0x0726  0x6800  0  0  8  0  0  0  0
tcblock mbipldin    0x01B2 0x1064 0x000A 0x0726 0x5000 \
                    0x6800 0x0000 0x0000 0x0008 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE11
#SETREGS R4206  10 0x0726  0x5800  0x6800  0  0  9  0  0  0  0
tcblock mbipldin    0x01B2 0x106E 0x000A 0x0726 0x5800 \
                    0x6800 0x0000 0x0000 0x0009 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE11B
#SETREGS R4216  10 0x2000  0x5804  0x6800  0  0  0xa  0  0  0  0
tcblock mbipldin    0x01B2 0x1078 0x000A 0x2000 0x5804 \
                    0x6800 0x0000 0x0000 0x000A 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE11C
#SETREGS R4226  10 0x3000  0x5808  0x6800  0  0  0xb  0  0  0  0
tcblock mbipldin    0x01B2 0x1082 0x000A 0x3000 0x5808 \
                    0x6800 0x0000 0x0000 0x000B 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE11D
#SETREGS R4236  10 0x4000  0x580C  0x6800  0  0  0xc  0  0  0  0
tcblock mbipldin    0x01B2 0x108C 0x000A 0x4000 0x580C \
                    0x6800 0x0000 0x0000 0x000C 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE12X
#SETREGS R4246  10 0x1000  0x6000  0x6800  0  0  9  0  0  0  0
tcblock mbipldin    0x01B2 0x1096 0x000A 0x1000 0x6000 \
                    0x6800 0x0000 0x0000 0x0009 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE12Y
#SETREGS R4256  10 0x0226  0x6001  0x6800  0  0  0xa  0  0  0  0
tcblock mbipldin    0x01B2 0x10A0 0x000A 0x0226 0x6001 \
                    0x6800 0x0000 0x0000 0x000A 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE12Z
#SETREGS R4266  10 0x0226  0x6005  0x6800  0  0  0xb  0  0  0  0
tcblock mbipldin    0x01B2 0x10AA 0x000A 0x0226 0x6005 \
                    0x6800 0x0000 0x0000 0x000B 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE13
#SETREGS R4276  10 0x0726  0x6800  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x10B4 0x000A 0x0726 0x6800 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE14
#SETREGS R4286  10 0x0726  0x7000  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x10BE 0x000A 0x0726 0x7000 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE15
#SETREGS R4296  10 0x0726  0x7800  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x10C8 0x000A 0x0726 0x7800 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE15B
#SETREGS R4306  10 0x2000  0x7804  0x6800  0  0  0xe  0  0  0  0
tcblock mbipldin    0x01B2 0x10D2 0x000A 0x2000 0x7804 \
                    0x6800 0x0000 0x0000 0x000E 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE15C
#SETREGS R4316  10 0x3000  0x7808  0x6800  0  0  0xf  0  0  0  0
tcblock mbipldin    0x01B2 0x10DC 0x000A 0x3000 0x7808 \
                    0x6800 0x0000 0x0000 0x000F 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE15D
#SETREGS R4326  10 0x4000  0x780C  0x6800  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x10E6 0x000A 0x4000 0x780C \
                    0x6800 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE16
#SETREGS R4336  10 0x1000  0x8000  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x10F0 0x000A 0x1000 0x8000 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE17
#SETREGS R4346  10 0x0726  0x8800  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x10FA 0x000A 0x0726 0x8800 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE18
#SETREGS R4356  10 0x0726  0x9000  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x1104 0x000A 0x0726 0x9000 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_PAGE19
#SETREGS R4366  10 0x0726  0x9800  0x6800  0  0  0xd  0  0  0  0
tcblock mbipldin    0x01B2 0x110E 0x000A 0x0726 0x9800 \
                    0x6800 0x0000 0x0000 0x000D 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_FUTURE1
#SETREGS R4376  10 0xFFFF  0xFFFF  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1118 0x000A 0xFFFF 0xFFFF \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_FUTURE2
#SETREGS R4386  10 0xFFFF  0xFFFF  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1122 0x000A 0xFFFF 0xFFFF \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_FUTURE3
#SETREGS R4396  10 0xFFFF  0xFFFF  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x112C 0x000A 0xFFFF 0xFFFF \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_FUTURE4
#SETREGS R4406  10 0xFFFF  0xFFFF  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1136 0x000A 0xFFFF 0xFFFF \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRP_HDECODE_FUTURE5
#SETREGS R4416  10 0xFFFF  0xFFFF  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1140 0x000A 0xFFFF 0xFFFF \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_HDECODE_PARAM
#SETREGS R4426   2 0  0
tcblock mbipldin    0x01B2 0x114A 0x0002 0x0000 0x0000 
#;
#;IPRL_HDECODE_PWORK
#SETREG R4428 0
tcblock mbipldin    0x0140 0x114C 0x0000 
#;
#;IPRP_HDECODE_WORK
#SETREG R4429 0
tcblock mbipldin    0x0140 0x114D 0x0000 
#;
#;IPRL_HDECODE_WORK3
#SETREGS R4430   3 0  0  0
tcblock mbipldin    0x01B2 0x114E 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;IPRP_HDECODE_ADDR
#SETREGS R4433   2 0  0
tcblock mbipldin    0x01B2 0x1151 0x0002 0x0000 0x0000 
#;
#;IPRL_HDECODE_LOOP
#SETREG R4435 0
tcblock mbipldin    0x0140 0x1153 0x0000 
#;
#;IPRL_HDECODE_COMP
#SETREG R4436 0
tcblock mbipldin    0x0140 0x1154 0x0000 
#;
#;IPRL_HEAD_WORK
#SETREGS R4437  10 0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1155 0x000A 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_HEAD_COPY
#SETREGS R4447   6 13:0x0000  0  0  0x226  0
tcblock mbipldin    0x01B2 0x115F 0x0006 0x0000 0x6800 \
                    0x0000 0x0000 0x0226 0x0000 
#;
#;IPRL_POS_550W
#SETREGS R4453   2 0x0226  0x0000
tcblock mbipldin    0x01B2 0x1165 0x0002 0x0226 0x0000 
#;
#;IPRL_NEG_550W
#SETREGS R4455   2 0xfdda  0xffff
tcblock mbipldin    0x01B2 0x1167 0x0002 0xFDDA 0xFFFF 
#;
#;IPRL_NEG_549W
#SETREGS R4457   2 0xfddb  0xffff
tcblock mbipldin    0x01B2 0x1169 0x0002 0xFDDB 0xFFFF 
#;
#;IPRL_EXTRACT_INST
#SETREGS R4459   8 0  0  0  0  0  0  0  R91
tcblock mbipldin    0x01B2 0x116B 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x005B 
#;
#;IPRL_EXTRACT_PARAM
#SETREGS R4467   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1173 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_EXTRACT_1024
#SETREGS R4473   6 0x100000L  1024  1024  1040  0x2000
tcblock mbipldin    0x01B2 0x1179 0x0006 0x0000 0x0010 \
                    0x0400 0x0400 0x0410 0x2000 
#;
#;IPRL_EXTRACT_512
#SETREGS R4479   6 0x040000L  512  512  1024  0x2800
tcblock mbipldin    0x01B2 0x117F 0x0006 0x0000 0x0004 \
                    0x0200 0x0200 0x0400 0x2800 
#;
#;IPRL_EXTRACT_256
#SETREGS R4485   6 0x010000L  256  256  1024  0x2400
tcblock mbipldin    0x01B2 0x1185 0x0006 0x0000 0x0001 \
                    0x0100 0x0100 0x0400 0x2400 
#;
#;IPRL_EXTRACT_128
#SETREGS R4491   6 0x004000L  128  128  1024  0x2C00
tcblock mbipldin    0x01B2 0x118B 0x0006 0x4000 0x0000 \
                    0x0080 0x0080 0x0400 0x2C00 
#;
#;IPRL_EXTRACT_1X10
#SETREGS R4497   6 0x020000L  128  1024  1024  0x2201
tcblock mbipldin    0x01B2 0x1191 0x0006 0x0000 0x0002 \
                    0x0080 0x0400 0x0400 0x2201 
#;
#;IPRL_EXTRACT_10X1
#SETREGS R4503   6 0x020000L  1024  128  1024  0x2202
tcblock mbipldin    0x01B2 0x1197 0x0006 0x0000 0x0002 \
                    0x0400 0x0080 0x0400 0x2202 
#;
#;IPRL_TAB_RECIP_FD
#SETREGS R4509   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x119D 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_TAB_RECIP_HR
#SETREGS R4515   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11A3 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_TAB_VEL_FD
#SETREGS R4521   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11A9 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_TAB_VEL_HR
#SETREGS R4527   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11AF 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_VEL_PARAM
#SETREGS R4533  12 0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11B5 0x000C 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_VEL_VER101
#SETREGS R4545  12 0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11C1 0x000C 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 
#;
#;IPRP_ADD_ADDR
#SETREGS R4557   3 0  0  0
tcblock mbipldin    0x01B2 0x11CD 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;IPRL_DL_PARAM
#SETREGS R4560   2 0  0
tcblock mbipldin    0x01B2 0x11D0 0x0002 0x0000 0x0000 
#;
#;IPRL_DL_LOOP
#SETREG R4562 0
tcblock mbipldin    0x0140 0x11D2 0x0000 
#;
#;IPRL_DL_NPAGE
#SETREG R4563 0
tcblock mbipldin    0x0140 0x11D3 0x0000 
#;
#;IPRL_DL_DLPAGE_LST
#SETREGS R4564   2 0x4000  0x4800
tcblock mbipldin    0x01B2 0x11D4 0x0002 0x4000 0x4800 
#;
#;IPRL_DL_DLPAGE
#SETREG R4566 0
tcblock mbipldin    0x0140 0x11D6 0x0000 
#;
#;IPRL_DL_INPAGE
#SETREG R4567 0
tcblock mbipldin    0x0140 0x11D7 0x0000 
#;
#;IPRP_DL_NWORDS_PNTR
#SETREG R4568 0
tcblock mbipldin    0x0140 0x11D8 0x0000 
#;
#;IPRL_DL_NWORDS
#SETREGS R4569   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11D9 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_DL_TEMP
#SETREG R4575 0
tcblock mbipldin    0x0140 0x11DF 0x0000 
#;
#;IPRL_DL_COPY
#SETREGS R4576   7 0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x11E0 0x0007 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_DL_CHECKED
#SETREG R4583 0
tcblock mbipldin    0x0140 0x11E7 0x0000 
#;
#;IPRL_DL_QADDR_REDO
#SETREG R4584 0
tcblock mbipldin    0x0140 0x11E8 0x0000 
#;
#;IPRL_BIN_PARAM
#SETREGS R4585   5 0  0  0  0  0
tcblock mbipldin    0x01B2 0x11E9 0x0005 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_BIN_ROWBIN2X2
#SETREGS R4590   6 19:0x0000  1024  2  1024  512
tcblock mbipldin    0x01B2 0x11EE 0x0006 0x0000 0x9800 \
                    0x0400 0x0002 0x0400 0x0200 
#;
#;IPRL_BIN_ROWBIN4X4
#SETREGS R4596   6 19:0x0000  1024  4  1024  256
tcblock mbipldin    0x01B2 0x11F4 0x0006 0x0000 0x9800 \
                    0x0400 0x0004 0x0400 0x0100 
#;
#;IPRL_BIN_ROWBIN8X8
#SETREGS R4602   6 19:0x0000  1024  8  1024  128
tcblock mbipldin    0x01B2 0x11FA 0x0006 0x0000 0x9800 \
                    0x0400 0x0008 0x0400 0x0080 
#;
#;IPRL_BIN_ROWBIN
#SETREGS R4608  11 0  0  19:0x0000  1024  4  1024  256  16  1  R81
tcblock mbipldin    0x01B2 0x1200 0x000B 0x0000 0x0000 \
                    0x0000 0x9800 0x0400 0x0004 0x0400 \
                    0x0100 0x0010 0x0001 0x1FF7 
#;
#;IPRL_BIN_LRBIN2X2
#SETREG R4619 0xFE60
tcblock mbipldin    0x0140 0x120B 0xFE60 
#;
#;IPRL_BIN_LRBIN4X4
#SETREG R4620 0xFE00
tcblock mbipldin    0x0140 0x120C 0xFE00 
#;
#;IPRL_BIN_LRBIN8X8
#SETREG R4621 0xFE30
tcblock mbipldin    0x0140 0x120D 0xFE30 
#;
#;IPRL_BIN_LRBIN
#SETREGS R4622   8 0x9800  0  0  0  4  14:0xFFE00  R8181
tcblock mbipldin    0x01B2 0x120E 0x0008 0x9800 0x0000 \
                    0x0000 0x0000 0x0004 0xFE00 0x700F \
                    0x1FF5 
#;
#;IPRL_BIN_LR_NWORDS
#SETREGS R4630   2 0  0
tcblock mbipldin    0x01B2 0x1216 0x0002 0x0000 0x0000 
#;
#;IPRL_BIN_DPC2X2
#SETREG R4632 0x4800
tcblock mbipldin    0x0140 0x1218 0x4800 
#;
#;IPRL_BIN_DPC4X4
#SETREG R4633 0x4400
tcblock mbipldin    0x0140 0x1219 0x4400 
#;
#;IPRL_BIN_DPC8X8
#SETREG R4634 0x4C00
tcblock mbipldin    0x0140 0x121A 0x4C00 
#;
#;IPRL_BIN_DPC
#SETREG R4635 0x4000
tcblock mbipldin    0x0140 0x121B 0x4000 
#;
#;IPRL_BIN_NWORDS
#SETREGS R4636   2 0  0
tcblock mbipldin    0x01B2 0x121C 0x0002 0x0000 0x0000 
#;
#;IPRL_BIN_DONE_ADDR
#SETREGS R4638   2 0  0
tcblock mbipldin    0x01B2 0x121E 0x0002 0x0000 0x0000 
#;
#;IPRL_TAPB_PAGELST
#SETREGS R4640  15 0x0800  0x1000  0x1800  0x2000  0x2800  0x3000 
tcblock mbipldin    0x01B2 0x1220 0x000F 0x0800 0x1000 \
                    0x1800 0x2000 0x2800 0x3000 0x3800 \
                    0x4800 0x5800 0x6800 0x7800 0x8800 \
                    0x9000 0x9800 0x0063 
#;
#;IPRL_TAPB_FRMNUM
#SETREG R4655 0
tcblock mbipldin    0x0140 0x122F 0x0000 
#;
#;IPRP_TAPB_PAGENUM
#SETREG R4656 0
tcblock mbipldin    0x0140 0x1230 0x0000 
#;
#;IPRL_TAPB_PAGENUM
#SETREGS R4657   3 0  0  0
tcblock mbipldin    0x01B2 0x1231 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;IPRL_TAPB_N_FRMS
#SETREG R4660 0
tcblock mbipldin    0x0140 0x1234 0x0000 
#;
#;IPRL_TAPB_Q_DL
#SETREG R4661 0
tcblock mbipldin    0x0140 0x1235 0x0000 
#;
#;IPRL_TAPB_TYPE
#SETREG R4662 0
tcblock mbipldin    0x0140 0x1236 0x0000 
#;
#;IPRL_TAPC_TYPE
#SETREG R4663 0
tcblock mbipldin    0x0140 0x1237 0x0000 
#;
#;IPRL_FLTGRAM_PARAM
#SETREGS R4664  11 0:0x0000  1:0x0000  1024  1024  1040  R8185  0 
tcblock mbipldin    0x01B2 0x1238 0x000B 0x0000 0x0000 \
                    0x0000 0x0800 0x0400 0x0400 0x0410 \
                    0x1FF9 0x0000 0x0000 0x0000 
#;
#;IPRL_FLTGRAM_GEN
#SETREGS R4675   3 0  0x0001  0x2000
tcblock mbipldin    0x01B2 0x1243 0x0003 0x0000 0x0001 \
                    0x2000 
#;
#;IPRL_FLTGRAM_TAPB
#SETREGS R4678   3 0  0x0002  0x2000
tcblock mbipldin    0x01B2 0x1246 0x0003 0x0000 0x0002 \
                    0x2000 
#;
#;IPRL_FLTGRAM_TAPC
#SETREGS R4681   3 0  0x0003  0x2000
tcblock mbipldin    0x01B2 0x1249 0x0003 0x0000 0x0003 \
                    0x2000 
#;
#;IPRL_10FLTGRAM_ADDR
#SETREGS R4684   3 0  0  0
tcblock mbipldin    0x01B2 0x124C 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;IPRL_10FLTGRAM_TYPE
#SETREG R4687 0
tcblock mbipldin    0x0140 0x124F 0x0000 
#;
#;IPRL_BIN_LR_OFFSET
#SETREGS R8181   2 0  0
tcblock mbipldin    0x01B2 0x1FF5 0x0002 0x0000 0x0000 
#;
#;IPRL_LONG_ZERO
#SETREGS R8183   2 0  0
tcblock mbipldin    0x01B2 0x1FF7 0x0002 0x0000 0x0000 
#;
#;IPRL_1024_OFFSET
#SETREGS R8185   2 1300L
tcblock mbipldin    0x01B2 0x1FF9 0x0002 0x0514 0x0000 
#;
#;IPRL_TLM_PAGE
#SETREG R8187 0
tcblock mbipldin    0x0140 0x1FFB 0x0000 
#;
#;IPRL_TLM_STATUS
#SETREG R8188 0
tcblock mbipldin    0x0140 0x1FFC 0x0000 
#;
#;IPRL_DEBUG_ADDR
#SETREG R8189 0
tcblock mbipldin    0x0140 0x1FFD 0x0000 
#;
#;IPRL_DEBUG_SKIP
#SETREG R8190 1
tcblock mbipldin    0x0140 0x1FFE 0x0001 
#;
#;IPRL_DL_REDUNDANT
#SETREG R0033 0
tcblock mbipldin    0x0140 0x0021 0x0000 
#;
#;IPRL_PURGELST_COUNT
#SETREG R0143 16
tcblock mbipldin    0x0140 0x008F 0x0010 
#;
#;IPRL_EXTRACT_OFFSET
#SETREGS R0091   2 393600L
tcblock mbipldin    0x01B2 0x005B 0x0002 0x0180 0x0006 
#;
#;IPRL_SEQ_FRMNUM
#SETREG R3072 0
tcblock mbipldin    0x0140 0x0C00 0x0000 
#;
#;IPRL_DL_VC_MODE
#SETREG R3075 2
tcblock mbipldin    0x0140 0x0C03 0x0002 
#;
#;IPRL_STR_MAG_TELEM
#SETREG R3077 2
tcblock mbipldin    0x0140 0x0C05 0x0002 
#;
#;IPRL_CB_ADDR
#SETREG R3104 0
tcblock mbipldin    0x0140 0x0C20 0x0000 
#;
#;IPRL_DMPMEM_PARAM
#SETREGS R3576   6 0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x0DF8 0x0006 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_JUNK_REG
#SETREGS R3568  16 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x0DF0 0x0010 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 
#;
#;QSR_CB_DONE_ADDR
#SETREG R4095 0
tcblock mbipldin    0x0140 0x0FFF 0x0000 
#;
#;IPRL_MAG_DLPAGES
#SETREGS R4688   2 0  0
tcblock mbipldin    0x01B2 0x1250 0x0002 0x0000 0x0000 
#;
#;IPRL_MAG_PGLEN1
#SETREGS R4690   2 0  0
tcblock mbipldin    0x01B2 0x1252 0x0002 0x0000 0x0000 
#;
#;IPRL_MAG_PGLEN2
#SETREGS R4692   2 0  0
tcblock mbipldin    0x01B2 0x1254 0x0002 0x0000 0x0000 
#;
#;IPRL_MAG_P1DP
#SETREG R4694 0
tcblock mbipldin    0x0140 0x1256 0x0000 
#;
#;IPRL_MAG_DLSETEP
#SETREG R4695 0
tcblock mbipldin    0x0140 0x1257 0x0000 
#;
#;IPRL_MAG_DLPAGE
#SETREG R4696 0
tcblock mbipldin    0x0140 0x1258 0x0000 
#;
#;IPRL_MAG_DLPLEN
#SETREGS R4697   2 0  0
tcblock mbipldin    0x01B2 0x1259 0x0002 0x0000 0x0000 
#=======================================================
#
# File: cam_reg2_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  9-Jan-1996 22:50:00.00
#; Input File: cam_reg2_v01.tab
#;
#;
#;IPRL_1FLT_PARAM
#SETREGS R4699   3 0  0x0000  0x0000
tcblock mbipldin    0x01B2 0x125B 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;IPRL_1FLT_DARK
#SETREGS R4702   3 0xe5  0x0004  0x0000
tcblock mbipldin    0x01B2 0x125E 0x0003 0x00E5 0x0004 \
                    0x0000 
#;
#;IPRL_1FLT_FD_CAL
#SETREGS R4705   3 0xe5  0x0005  0x0000
tcblock mbipldin    0x01B2 0x1261 0x0003 0x00E5 0x0005 \
                    0x0000 
#;
#;IPRL_1FLT_HR_CAL
#SETREGS R4708   3 0xe5  0x0006  0x0000
tcblock mbipldin    0x01B2 0x1264 0x0003 0x00E5 0x0006 \
                    0x0000 
#;
#;IPRL_1FLT_COPYD
#SETREGS R4711   6 0:0x00fc  13:0x0726  1074320L
tcblock mbipldin    0x01B2 0x1267 0x0006 0x00FC 0x0000 \
                    0x0726 0x6800 0x6490 0x0010 
#=======================================================
#
# File: cam_reg3_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 11-Jan-1996 15:03:56.00
#; Input File: cam_reg3_v01.tab
#;
#;
#;IPRL_COMP_PARAM
#SETREGS R4717   3 0xe5  0x0004  0x0000
tcblock mbipldin    0x01B2 0x126D 0x0003 0x00E5 0x0004 \
                    0x0000 
#;
#;IPRL_COMP_SQRT
#SETREGS R4720   8 1:0x0226  2:0x0226  0x100000L  0  9
tcblock mbipldin    0x01B2 0x1270 0x0008 0x0226 0x0800 \
                    0x0226 0x1000 0x0000 0x0010 0x0000 \
                    0x0009 
#=======================================================
#
# File: cam_reg4_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 18-Jan-1996 22:23:40.00
#; Input File: cam_reg4_v01.tab
#;
#;
#;IPRL_MAG_PARAM
#SETREGS R4728  14 0  0  0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1278 0x000E 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 
#=======================================================
#
# File: cam_reg5_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 23-Jan-1996 02:38:54.00
#; Input File: cam_reg5_v01.tab
#;
#;
#;IPRL_VEL_PARAM
#SETREGS R5001  15 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x1389 0x000F 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_VEL_SCALE
#SETREGS R5016   8 13:0x0726  0  0  0x100000L  0  0
tcblock mbipldin    0x01B2 0x1398 0x0008 0x0726 0x6800 \
                    0x0000 0x0000 0x0000 0x0010 0x0000 \
                    0x0000 
#=======================================================
#
# File: cam_reg4b.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 29-Jan-1996 22:51:54.00
#; Input File: cam_reg4b.reg
#;
#;
#;IPRL_TAB_RECIP_FD
#SETREGS R4509   5 0x8000  0x0009  0x0000  0x800a  4
tcblock mbipldin    0x01B2 0x119D 0x0005 0x8000 0x0009 \
                    0x0000 0x800A 0x0004 
#;
#;IPRL_TAB_RECIP_HR
#SETREGS R4515   5 0x8000  0x0009  0x0000  0x800a  4
tcblock mbipldin    0x01B2 0x11A3 0x0005 0x8000 0x0009 \
                    0x0000 0x800A 0x0004 
#;
#;IPRL_TAB_VEL_FD
#SETREGS R4521   5 0  0x000b  0x8000  0x800a  4
tcblock mbipldin    0x01B2 0x11A9 0x0005 0x0000 0x000B \
                    0x8000 0x800A 0x0004 
#;
#;IPRL_TAB_VEL_HR
#SETREGS R4527   5 0  0x000b  0x8000  0x800a  4
tcblock mbipldin    0x01B2 0x11AF 0x0005 0x0000 0x000B \
                    0x8000 0x800A 0x0004 
#=======================================================
#
# File: cam_reg6_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  1-Mar-1996 17:08:59.00
#; Input File: cam_reg6_v01.reg
#;
#;
#;IPRL_SUMDIFF_PARAM
#SETREGS R5024  10 0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13A0 0x000A 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_SUMDIFF_WORK
#SETREGS R5034  11 0:0x0  0:0x0  0:0x0  0x100000L  1  1  16
tcblock mbipldin    0x01B2 0x13AA 0x000B 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0010 0x0001 0x0001 0x0010 
#;
#;IPRL_SQRT_PARAM
#SETREGS R5045   8 0:0x0  0:0x0  0x100000L  0  9
tcblock mbipldin    0x01B2 0x13B5 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0010 0x0000 \
                    0x0009 
#;
#;IPRL_SQRT_OLDHEAD
#SETREGS R5053  10 0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13BD 0x000A 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_FLTGRAM_SD
#SETREGS R5063   3 0xe5  0x0009  0x2000
tcblock mbipldin    0x01B2 0x13C7 0x0003 0x00E5 0x0009 \
                    0x2000 
#;
#;IPRL_FLTGRAM_SI
#SETREGS R5066   3 0xe5  0x000a  0x2000
tcblock mbipldin    0x01B2 0x13CA 0x0003 0x00E5 0x000A \
                    0x2000 
#;
#;IPRL_LDEP_PARAM
#SETREGS R5069  12 0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13CD 0x000C 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 
#;
#;IPRL_CONT_PARAM
#SETREGS R5081  13 0  0  0  0  0  0  0  0  0  0  0  0  0
tcblock mbipldin    0x01B2 0x13D9 0x000D 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 
#;
#;IPRL_CONT_WORK
#SETREGS R5094  10 17:0x0726  0  0  18:0x0726  0  0  0  0
tcblock mbipldin    0x01B2 0x13E6 0x000A 0x0726 0x8800 \
                    0x0000 0x0000 0x0726 0x9000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;IPRL_EXTRACT_80K
#SETREGS R5104   6 0x0c8000L  1024  800  1024  0x2e00
tcblock mbipldin    0x01B2 0x13F0 0x0006 0x8000 0x000C \
                    0x0400 0x0320 0x0400 0x2E00 
#;
#;IPRL_EXTRACT_300
#SETREGS R5110   6 0x15f90L  1024  300  300  0x2f00
tcblock mbipldin    0x01B2 0x13F6 0x0006 0x5F90 0x0001 \
                    0x0400 0x012C 0x012C 0x2F00 
#;
#;IPRL_EXTRACT_350
#SETREGS R5116   6 0x1de84L  1024  350  350  0x2f01
tcblock mbipldin    0x01B2 0x13FC 0x0006 0xDE84 0x0001 \
                    0x0400 0x015E 0x015E 0x2F01 
#;
#;IPRL_EXTRACT_400
#SETREGS R5122   6 0x27100L  1024  400  400  0x2f02
tcblock mbipldin    0x01B2 0x1402 0x0006 0x7100 0x0002 \
                    0x0400 0x0190 0x0190 0x2F02 
#;
#;IPRL_EXTRACT_450
#SETREGS R5128   6 0x31704L  1024  450  450  0x2f03
tcblock mbipldin    0x01B2 0x1408 0x0006 0x1704 0x0003 \
                    0x0400 0x01C2 0x01C2 0x2F03 
#;
#;IPRL_EXTRACT_550
#SETREGS R5134   6 0x49da4L  1024  550  550  0x2f04
tcblock mbipldin    0x01B2 0x140E 0x0006 0x9DA4 0x0004 \
                    0x0400 0x0226 0x0226 0x2F04 
#=======================================================
#
# File: cam_reg6b_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  5-Mar-1996 16:07:54.00
#; Input File: cam_reg6b_v01.reg
#;
#;
#;IPRL_EXTRACT_300
#SETREGS R5110   6 0x15f90L  300  300  1024  0x2100
tcblock mbipldin    0x01B2 0x13F6 0x0006 0x5F90 0x0001 \
                    0x012C 0x012C 0x0400 0x2100 
#;
#;IPRL_EXTRACT_350
#SETREGS R5116   6 0x1de84L  350  350  1024  0x2300
tcblock mbipldin    0x01B2 0x13FC 0x0006 0xDE84 0x0001 \
                    0x015E 0x015E 0x0400 0x2300 
#;
#;IPRL_EXTRACT_400
#SETREGS R5122   6 0x27100L  400  400  1024  0x2500
tcblock mbipldin    0x01B2 0x1402 0x0006 0x7100 0x0002 \
                    0x0190 0x0190 0x0400 0x2500 
#;
#;IPRL_EXTRACT_450
#SETREGS R5128   6 0x31704L  450  450  1024  0x2700
tcblock mbipldin    0x01B2 0x1408 0x0006 0x1704 0x0003 \
                    0x01C2 0x01C2 0x0400 0x2700 
#;
#;IPRL_EXTRACT_550
#SETREGS R5134   6 0x49da4L  550  550  1024  0x2900
tcblock mbipldin    0x01B2 0x140E 0x0006 0x9DA4 0x0004 \
                    0x0226 0x0226 0x0400 0x2900 
#=======================================================
#
# File: cam_reg30_v03.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 19-Apr-1996 04:31:51.00
#; Input File: cam_reg30_v03.reg
#;
#;
#;iprl_fd_contflt
#SETREGS R5140   3 0xe5  0x404b  0x2000
tcblock mbipldin    0x01B2 0x1414 0x0003 0x00E5 0x404B \
                    0x2000 
#;
#;iprl_pdump_n
#SETREG R5143 2
tcblock mbipldin    0x0140 0x1417 0x0002 
#;
#;iprl_pdump_list
#SETREGS R5144  10 0x5000  0x5009  0x6000  0x6009  0x7000  0x7009 
tcblock mbipldin    0x01B2 0x1418 0x000A 0x5000 0x5009 \
                    0x6000 0x6009 0x7000 0x7009 0x8000 \
                    0x8009 0x0000 0x0000 
#;
#;iprl_pdump_counter
#SETREG R5154 0
tcblock mbipldin    0x0140 0x1422 0x0000 
#;
#;iprp_pdump_pointer
#SETREG R5155 0
tcblock mbipldin    0x0140 0x1423 0x0000 
#;
#;iprl_pdump_page
#SETREGS R5156   3 0  0  0
tcblock mbipldin    0x01B2 0x1424 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_pdump_copyd
#SETREGS R5159   6 0  0  13:0x0726  589824L
tcblock mbipldin    0x01B2 0x1427 0x0006 0x0000 0x0000 \
                    0x0726 0x6800 0x0000 0x0009 
#=======================================================
#
# File: cam_reg30b_v03.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 19-Apr-1996 04:32:07.00
#; Input File: cam_reg30b_v03.reg
#;
#;
#;iprl_1flt_dark
#SETREGS R4702   3 0xe5  0x4044  0x0000
tcblock mbipldin    0x01B2 0x125E 0x0003 0x00E5 0x4044 \
                    0x0000 
#;
#;iprl_1flt_fd_cal
#SETREGS R4705   3 0xe5  0x4045  0x0000
tcblock mbipldin    0x01B2 0x1261 0x0003 0x00E5 0x4045 \
                    0x0000 
#;
#;iprl_1flt_hr_cal
#SETREGS R4708   3 0xe5  0x4046  0x0000
tcblock mbipldin    0x01B2 0x1264 0x0003 0x00E5 0x4046 \
                    0x0000 
#;
#;iprl_tab_vel_fd
#SETREGS R4521   5 0x8000  0x0002  0x8000  0x800a  4
tcblock mbipldin    0x01B2 0x11A9 0x0005 0x8000 0x0002 \
                    0x8000 0x800A 0x0004 
#;
#;iprl_tab_vel_hr
#SETREGS R4527   5 0x8000  0x0002  0x8000  0x800a  4
tcblock mbipldin    0x01B2 0x11AF 0x0005 0x8000 0x0002 \
                    0x8000 0x800A 0x0004 
#;
#;iprl_fltgram_tapb
#SETREGS R4678   3 0xe5  0x0002  0x2000
tcblock mbipldin    0x01B2 0x1246 0x0003 0x00E5 0x0002 \
                    0x2000 
#=======================================================
#
# File: cam_reg_full1_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  2-May-1996 18:10:39.00
#; Input File: cam_reg_full1_v01.reg
#;
#;
#;iprl_1flt_dark
#SETREGS R4702   3 0xe5  0x4044  0xb000
tcblock mbipldin    0x01B2 0x125E 0x0003 0x00E5 0x4044 \
                    0xB000 
#;
#;iprl_1flt_fd_cal
#SETREGS R4705   3 0xe5  0x4045  0xb000
tcblock mbipldin    0x01B2 0x1261 0x0003 0x00E5 0x4045 \
                    0xB000 
#;
#;iprl_1flt_hr_cal
#SETREGS R4708   3 0xe5  0x4046  0xb000
tcblock mbipldin    0x01B2 0x1264 0x0003 0x00E5 0x4046 \
                    0xB000 
#=======================================================
#
# File: cam_reg31_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  2-May-1996 18:23:23.00
#; Input File: cam_reg31_v01.reg
#;
#;
#;iprl_focus3_pages
#SETREGS R5165  16 1:0x0226  2:0x0226  3:0x0226  4:0x0726  15:0x07
tcblock mbipldin    0x01B2 0x142D 0x0010 0x0226 0x0800 \
                    0x0226 0x1000 0x0226 0x1800 0x0726 \
                    0x2000 0x0726 0x7800 0x3000 0x7808 \
                    0x0726 0x9000 0x0726 0x9800 
#;
#;iprl_focus3_value2
#SETREG R5181 2
tcblock mbipldin    0x0140 0x143D 0x0002 
#;
#;iprp_focus3_page
#SETREG R5182 0
tcblock mbipldin    0x0140 0x143E 0x0000 
#;
#;iprl_focus3_tmp_page
#SETREGS R5183   3 0  0  0
tcblock mbipldin    0x01B2 0x143F 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_extract3_offsets
#SETREGS R5186   6 0x16000L  0x76000L  0xd6000L
tcblock mbipldin    0x01B2 0x1442 0x0006 0x6000 0x0001 \
                    0x6000 0x0007 0x6000 0x000D 
#;
#;iprl_extract3_instr
#SETREGS R5192   8 0  0  0  0  1024  80  1024          5186
tcblock mbipldin    0x01B2 0x1448 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0400 0x0050 0x0400 \
                    0x1442 
#;
#;iprl_extract3_param
#SETREGS R5200   5 0x3c000L  0xe2  0x404f  0xb001
tcblock mbipldin    0x01B2 0x1450 0x0005 0xC000 0x0003 \
                    0x00E2 0x404F 0xB001 
#=======================================================
#
# File: cam_reg32_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  6-May-1996 15:03:11.00
#; Input File: cam_reg32_v01.reg
#;
#;
#;iprl_extract_60k
#SETREGS R5205   6 0x096000L  1024  600  1024  0x2a00
tcblock mbipldin    0x01B2 0x1455 0x0006 0x6000 0x0009 \
                    0x0400 0x0258 0x0400 0x2A00 
#=======================================================
#
# File: cam_reg32b_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  6-May-1996 21:07:19.00
#; Input File: cam_reg32b_v01.reg
#;
#;
#;iprl_pdump_n
#SETREG R5143 8
tcblock mbipldin    0x0140 0x1417 0x0008 
#=======================================================
#
# File: cam_reg34_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  9-May-1996 19:11:36.00
#; Input File: cam_reg34_v01.reg
#;
#;
#;iprl_extract_64k
#SETREGS R5211   6 0x0a0000L  1024  640  1024  0x2b00
tcblock mbipldin    0x01B2 0x145B 0x0006 0x0000 0x000A \
                    0x0400 0x0280 0x0400 0x2B00 
#=======================================================
#
# File: cam_reg35_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 10-May-1996 00:01:27.00
#; Input File: cam_reg35_v01.reg
#;
#;
#;iprp_hdecode_page4
#SETREGS R4136  10 4:0x0226  0x6800  0  0  5  0  0  0  0
tcblock mbipldin    0x01B2 0x1028 0x000A 0x0226 0x2000 \
                    0x6800 0x0000 0x0000 0x0005 0x0000 \
                    0x0000 0x0000 0x0000 
#=======================================================
#
# File: cam_reg37_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 15-May-1996 01:55:43.00
#; Input File: cam_reg37_v01.reg
#;
#;
#;iprp_hdecode_page14y
#SETREGS R4256  10 0x6226  0x7006  0x6800  0  0  0xa  0  0  0  0
tcblock mbipldin    0x01B2 0x10A0 0x000A 0x6226 0x7006 \
                    0x6800 0x0000 0x0000 0x000A 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;iprp_hdecode_page14z
#SETREGS R4266  10 0xb226  0x7008  0x6800  0  0  0xb  0  0  0  0
tcblock mbipldin    0x01B2 0x10AA 0x000A 0xB226 0x7008 \
                    0x6800 0x0000 0x0000 0x000B 0x0000 \
                    0x0000 0x0000 0x0000 
#=======================================================
#
# File: cam_reg38_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 20-May-1996 17:46:24.00
#; Input File: cam_reg38_v01.reg
#;
#;
#;iprp_hdecode_page13b
#SETREGS R4376  10 0x2000  0x6804  0x6800  0  0  0xa  0  0  0  0
tcblock mbipldin    0x01B2 0x1118 0x000A 0x2000 0x6804 \
                    0x6800 0x0000 0x0000 0x000A 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;iprp_hdecode_page13c
#SETREGS R4386  10 0x3000  0x6808  0x6800  0  0  0xb  0  0  0  0
tcblock mbipldin    0x01B2 0x1122 0x000A 0x3000 0x6808 \
                    0x6800 0x0000 0x0000 0x000B 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;iprp_hdecode_page13d
#SETREGS R4396  10 0x4000  0x680C  0x6800  0  0  0xc  0  0  0  0
tcblock mbipldin    0x01B2 0x112C 0x000A 0x4000 0x680C \
                    0x6800 0x0000 0x0000 0x000C 0x0000 \
                    0x0000 0x0000 0x0000 
#=======================================================
#
# File: cam_reg39_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 23-May-1996 03:01:36.00
#; Input File: cam_reg39_v01.reg
#;
#;
#;iprl_set_ext_param
#SETREG R5217 0
tcblock mbipldin    0x0140 0x1461 0x0000 
#;
#;iprl_set_ext_low
#SETREG R5218 0
tcblock mbipldin    0x0140 0x1462 0x0000 
#;
#;iprl_set_ext_high
#SETREG R5219 0
tcblock mbipldin    0x0140 0x1463 0x0000 
#;
#;iprl_value_0003
#SETREG R5220 0x0003
tcblock mbipldin    0x0140 0x1464 0x0003 
#;
#;iprl_value_fffc
#SETREG R5221 0xfffc
tcblock mbipldin    0x0140 0x1465 0xFFFC 
#;
#;iprl_value_0100
#SETREG R5222 0x0100
tcblock mbipldin    0x0140 0x1466 0x0100 
#;
#;iprl_value_0001
#SETREG R5223 0x0001
tcblock mbipldin    0x0140 0x1467 0x0001 
#;
#;iprl_ltc30_count
#SETREG R5224 -1
tcblock mbipldin    0x0140 0x1468 0xFFFF 
#;
#;iprl_dark30_count
#SETREG R5225 -1
tcblock mbipldin    0x0140 0x1469 0xFFFF 
#=======================================================
#
# File: cam_reg41_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 24-Jul-1996 03:18:08.00
#; Input File: cam_reg41_v01.reg
#;
#;
#;iprl_focus3_pages (first half)
#SETREGS R5165   8 1:0x0226  2:0x0226  3:0x0226  4:0x0226
tcblock mbipldin    0x01B2 0x142D 0x0008 0x0226 0x0800 \
                    0x0226 0x1000 0x0226 0x1800 0x0226 \
                    0x2000 
#;
#;iprl_focus3_pages (second half)
#SETREGS R5173   8 15:0x0726  15:0x83000  18:0x0726  19:0x0726
tcblock mbipldin    0x01B2 0x1435 0x0008 0x0726 0x7800 \
                    0x3000 0x7808 0x0726 0x9000 0x0726 \
                    0x9800 
#;
#;iprl_pdump_n
#SETREG R5143 8
tcblock mbipldin    0x0140 0x1417 0x0008 
#=======================================================
#
# File: cam_reg42_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 25-Jul-1996 14:34:38.00
#; Input File: cam_reg42_v01.reg
#;
#;
#;iprl_crop_param (first half)
#SETREGS R5226   4 0:0x0  0:0x0
tcblock mbipldin    0x01B2 0x146A 0x0004 0x0000 0x0000 \
                    0x0000 0x0000 
#;
#;iprl_crop_param (second half)
#SETREGS R5230   5 0:0x0  0  0L
tcblock mbipldin    0x01B2 0x146E 0x0005 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;iprl_crop_offset
#SETREGS R5235   2 0  0
tcblock mbipldin    0x01B2 0x1473 0x0002 0x0000 0x0000 
#;
#;iprl_crop_instr
#SETREGS R5237   8 0  0  0  0  1024  0  0          5235
tcblock mbipldin    0x01B2 0x1475 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0400 0x0000 0x0000 \
                    0x1473 
#;
#;iprl_crop_rad504
#SETREGS R5245   5 14:0x00000  0x0fc0  798020L
tcblock mbipldin    0x01B2 0x147D 0x0005 0x0000 0x7000 \
                    0x0FC0 0x2D44 0x000C 
#;
#;iprl_crop_rad480
#SETREGS R5250   5 14:0x50000  0x0f00  723816L
tcblock mbipldin    0x01B2 0x1482 0x0005 0x0000 0x7005 \
                    0x0F00 0x0B68 0x000B 
#;
#;iprl_vlcm_cont_flt
#SETREGS R5255   3 0  0  0
tcblock mbipldin    0x01B2 0x1487 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_cont
#SETREGS R5258   3 0  0  0
tcblock mbipldin    0x01B2 0x148A 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_vel
#SETREGS R5261   3 0  0  0
tcblock mbipldin    0x01B2 0x148D 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_ldepth
#SETREGS R5264   3 0  0  0
tcblock mbipldin    0x01B2 0x1490 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_mag
#SETREGS R5267   3 0  0  0
tcblock mbipldin    0x01B2 0x1493 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_store_scale
#SETREGS R5270   8 5:0x000000  15:0x0726  0x100000L  1  13
tcblock mbipldin    0x01B2 0x1496 0x0008 0x0000 0x2800 \
                    0x0726 0x7800 0x0000 0x0010 0x0001 \
                    0x000D 
#;
#;iprl_store_header
#SETREGS R5278   6 19:0x110000  15:0x0500  550L
tcblock mbipldin    0x01B2 0x149E 0x0006 0x0000 0x9811 \
                    0x0500 0x7800 0x0226 0x0000 
#;
#;iprl_storev_scale
#SETREGS R5284   8 5:0x000000  15:0x0726  0x100000L  1  13
tcblock mbipldin    0x01B2 0x14A4 0x0008 0x0000 0x2800 \
                    0x0726 0x7800 0x0000 0x0010 0x0001 \
                    0x000D 
#;
#;iprl_storev_header
#SETREGS R5292   6 19:0x110000  15:0x0500  550L
tcblock mbipldin    0x01B2 0x14AC 0x0006 0x0000 0x9811 \
                    0x0500 0x7800 0x0226 0x0000 
#;
#;iprl_storec_scale
#SETREGS R5298   8 7:0x000000  15:0x0726  0x100000L  1  16
tcblock mbipldin    0x01B2 0x14B2 0x0008 0x0000 0x3800 \
                    0x0726 0x7800 0x0000 0x0010 0x0001 \
                    0x0010 
#;
#;iprl_storec_header
#SETREGS R5306   6 19:0x110226  15:0x0500  550L
tcblock mbipldin    0x01B2 0x14BA 0x0006 0x0226 0x9811 \
                    0x0500 0x7800 0x0226 0x0000 
#;
#;iprl_store_move2
#SETREGS R5312   6 15:0x000500  11:0x0500  0x100226L
tcblock mbipldin    0x01B2 0x14C0 0x0006 0x0500 0x7800 \
                    0x0500 0x5800 0x0226 0x0010 
#;
#;iprl_sqrt_dpc_low
#SETREG R5318 0
tcblock mbipldin    0x0140 0x14C6 0x0000 
#;
#;iprl_std_fmt_vel
#SETREGS R5319   4 7:0x0726  13:0x0726
tcblock mbipldin    0x01B2 0x14C7 0x0004 0x0726 0x3800 \
                    0x0726 0x6800 
#;
#;iprl_std_fmt_ldep
#SETREGS R5323   4 6:0x0726  4:0x0226
tcblock mbipldin    0x01B2 0x14CB 0x0004 0x0726 0x3000 \
                    0x0226 0x2000 
#;
#;iprl_std_fmt_cont
#SETREGS R5327   4 5:0x0726  4:0x0226
tcblock mbipldin    0x01B2 0x14CF 0x0004 0x0726 0x2800 \
                    0x0226 0x2000 
#;
#;iprl_std_fmt_contf
#SETREGS R5331   4 19:0x0726  4:0x0226
tcblock mbipldin    0x01B2 0x14D3 0x0004 0x0726 0x9800 \
                    0x0226 0x2000 
#;
#;iprl_std_fmt_mag
#SETREGS R5335   4 17:0x0726  18:0x0726
tcblock mbipldin    0x01B2 0x14D7 0x0004 0x0726 0x8800 \
                    0x0726 0x9000 
#;
#;iprl_std_fmt_pcont
#SETREGS R5339   4 11:0x0726  18:0x0726
tcblock mbipldin    0x01B2 0x14DB 0x0004 0x0726 0x5800 \
                    0x0726 0x9000 
#;
#;iprl_std_fmt_pvel
#SETREGS R5343   4 11:0x0726  15:0x0726
tcblock mbipldin    0x01B2 0x14DF 0x0004 0x0726 0x5800 \
                    0x0726 0x7800 
#;
#;iprl_extract_50k
#SETREGS R5347   6 512000L  1024  500  1024  0x2d00
tcblock mbipldin    0x01B2 0x14E3 0x0006 0xD000 0x0007 \
                    0x0400 0x01F4 0x0400 0x2D00 
#;
#;iprl_extract_85k
#SETREGS R5353   6 870400L  1024  850  1024  0x2f00
tcblock mbipldin    0x01B2 0x14E9 0x0006 0x4800 0x000D \
                    0x0400 0x0352 0x0400 0x2F00 
#;
#;iprl_extract_75k
#SETREGS R5359   6 768000L  1024  750  1024  0x2040
tcblock mbipldin    0x01B2 0x14EF 0x0006 0xB800 0x000B \
                    0x0400 0x02EE 0x0400 0x2040 
#;
#;iprl_extract_70k
#SETREGS R5365   6 716800L  1024  700  1024  0x2140
tcblock mbipldin    0x01B2 0x14F5 0x0006 0xF000 0x000A \
                    0x0400 0x02BC 0x0400 0x2140 
#=======================================================
#
# File: cam_reg42r_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 25-Jul-1996 14:34:55.00
#; Input File: cam_reg42r_v01.reg
#;
#;
#;iprl_bin_rowbin2x2
#SETREGS R4590   6 4:0x0000  1024  2  1024  512
tcblock mbipldin    0x01B2 0x11EE 0x0006 0x0000 0x2000 \
                    0x0400 0x0002 0x0400 0x0200 
#;
#;iprl_bin_rowbin4x4
#SETREGS R4596   6 4:0x0000  1024  4  1024  256
tcblock mbipldin    0x01B2 0x11F4 0x0006 0x0000 0x2000 \
                    0x0400 0x0004 0x0400 0x0100 
#;
#;iprl_bin_rowbin8x8
#SETREGS R4602   6 4:0x0000  1024  8  1024  128
tcblock mbipldin    0x01B2 0x11FA 0x0006 0x0000 0x2000 \
                    0x0400 0x0008 0x0400 0x0080 
#;
#;iprl_bin_lrbin
#SETREGS R4622   8 0x2000  0  0  0  4  14:0xFFE00  R8181
tcblock mbipldin    0x01B2 0x120E 0x0008 0x2000 0x0000 \
                    0x0000 0x0000 0x0004 0xFE00 0x700F \
                    0x1FF5 
#;
#;iprl_pdump_list (first half)
#SETREGS R5144   5 0x6000  0x6009  0x7000  0x7009  0x8000
tcblock mbipldin    0x01B2 0x1418 0x0005 0x6000 0x6009 \
                    0x7000 0x7009 0x8000 
#;
#;iprl_pdump_list (second half)
#SETREGS R5149   5 0x8009  0x5000  0x5009  0  0
tcblock mbipldin    0x01B2 0x141D 0x0005 0x8009 0x5000 \
                    0x5009 0x0000 0x0000 
#;
#;iprl_pdump_n
#SETREG R5143 6
tcblock mbipldin    0x0140 0x1417 0x0006 
#=======================================================
#
# File: cam_reg43_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  5-Aug-1996 22:22:12.00
#; Input File: cam_reg43_v01.reg
#;
#;
#;iprl_ext_hr_ve_fe_me
#SETREGS R5371   6 512000L  1024  500  1024  0x2d00
tcblock mbipldin    0x01B2 0x14FB 0x0006 0xD000 0x0007 \
                    0x0400 0x01F4 0x0400 0x2D00 
#;
#;iprl_ext_hr_fe_me_v2
#SETREGS R5377   6 0x0a0000L  1024  640  1024  0x2b00
tcblock mbipldin    0x01B2 0x1501 0x0006 0x0000 0x000A \
                    0x0400 0x0280 0x0400 0x2B00 
#;
#;iprl_bin_k_shift
#SETREG R5383 0
tcblock mbipldin    0x0140 0x1507 0x0000 
#=======================================================
#
# File: cam_reg45_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 22-Aug-1996 23:28:35.00
#; Input File: cam_reg45_v01.reg
#;
#;
#;iprl_fltgram_c_param
#SETREGS R5384   4 0  0  0  0
tcblock mbipldin    0x01B2 0x1508 0x0004 0x0000 0x0000 \
                    0x0000 0x0000 
#;
#;iprl_1flt_full_dark
#SETREGS R5388   3 0xe5  0x4052  0xb000
tcblock mbipldin    0x01B2 0x150C 0x0003 0x00E5 0x4052 \
                    0xB000 
#;
#;iprl_1flt_phase_div
#SETREGS R5391   3 0xe3  0x4053  0x2000
tcblock mbipldin    0x01B2 0x150F 0x0003 0x00E3 0x4053 \
                    0x2000 
#;
#;iprl_1flt_full_ltc
#SETREGS R5394   3 0xe5  0x4054  0xb000
tcblock mbipldin    0x01B2 0x1512 0x0003 0x00E5 0x4054 \
                    0xB000 
#;
#;iprl_ext_phase_div
#SETREGS R5397   6 870400L  1024  850  1024  0x2f00
tcblock mbipldin    0x01B2 0x1515 0x0006 0x4800 0x000D \
                    0x0400 0x0352 0x0400 0x2F00 
#=======================================================
#
# File: cam_reg47r_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  5-Sep-1996 02:34:09.00
#; Input File: cam_reg47r_v01.reg
#;
#;
#;iprl_bin_rowbin2x2
#SETREGS R4590   6 10:0x0000  1024  2  1024  512
tcblock mbipldin    0x01B2 0x11EE 0x0006 0x0000 0x5000 \
                    0x0400 0x0002 0x0400 0x0200 
#;
#;iprl_bin_rowbin4x4
#SETREGS R4596   6 10:0x0000  1024  4  1024  256
tcblock mbipldin    0x01B2 0x11F4 0x0006 0x0000 0x5000 \
                    0x0400 0x0004 0x0400 0x0100 
#;
#;iprl_bin_rowbin8x8
#SETREGS R4602   6 10:0x0000  1024  8  1024  128
tcblock mbipldin    0x01B2 0x11FA 0x0006 0x0000 0x5000 \
                    0x0400 0x0008 0x0400 0x0080 
#;
#;iprl_bin_lrbin
#SETREGS R4622   8 0x5000  0  0  0  4  14:0xFFE00  R8181
tcblock mbipldin    0x01B2 0x120E 0x0008 0x5000 0x0000 \
                    0x0000 0x0000 0x0004 0xFE00 0x700F \
                    0x1FF5 
#=======================================================
#
# File: cam_reg49_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  7-Oct-1996 23:41:58.00
#; Input File: cam_reg49_v01.reg
#;
#;
#;iprl_track_nmin
#SETREG R5403 4
tcblock mbipldin    0x0140 0x151B 0x0004 
#;
#;iprl_track_npix
#SETREG R5404 1
tcblock mbipldin    0x0140 0x151C 0x0001 
#;
#;iprl_track_npix_max
#SETREG R5405 500
tcblock mbipldin    0x0140 0x151D 0x01F4 
#;
#;iprl_track_imin
#SETREG R5406 6
tcblock mbipldin    0x0140 0x151E 0x0006 
#;
#;iprl_track_extract
#SETREGS R5407   2 0  0
tcblock mbipldin    0x01B2 0x151F 0x0002 0x0000 0x0000 
#;
#;iprl_track_offset
#SETREG R5409 498
tcblock mbipldin    0x0140 0x1521 0x01F2 
#;
#;iprl_ext_hr_t_ve_fe_me
#SETREGS R5410   6 512000L  500  1024  1024  0x2d01
tcblock mbipldin    0x01B2 0x1522 0x0006 0xD000 0x0007 \
                    0x01F4 0x0400 0x0400 0x2D01 
#;
#;iprl_ext_hr_t_fe_me_v2
#SETREGS R5416   6 0x0a0000L  640  1024  1024  0x2b01
tcblock mbipldin    0x01B2 0x1528 0x0006 0x0000 0x000A \
                    0x0280 0x0400 0x0400 0x2B01 
#=======================================================
#
# File: cam_reg50_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  7-Oct-1996 23:44:13.00
#; Input File: cam_reg50_v01.reg
#;
#;
#;iprl_magcam_do_align
#SETREG R5422 0
tcblock mbipldin    0x0140 0x152E 0x0000 
#;
#;iprl_magcam_yalign
#SETREGS R5423   8 1:0x0000  17:0x0000  1024  655  1024  128
tcblock mbipldin    0x01B2 0x152F 0x0008 0x0000 0x0800 \
                    0x0000 0x8800 0x0400 0x028F 0x0400 \
                    0x0080 
#;
#;iprl_magcam_move1a
#SETREGS R5431   6 2:0x0226  1:0x0000  0x100000L
tcblock mbipldin    0x01B2 0x1537 0x0006 0x0226 0x1000 \
                    0x0000 0x0800 0x0000 0x0010 
#;
#;iprl_magcam_move1b
#SETREGS R5437   6 2:0x0226  17:0x0000  0x100000L
tcblock mbipldin    0x01B2 0x153D 0x0006 0x0226 0x1000 \
                    0x0000 0x8800 0x0000 0x0010 
#;
#;iprl_magcam_move2
#SETREGS R5443   6 17:0x0000  2:0x0226  0x100000L
tcblock mbipldin    0x01B2 0x1543 0x0006 0x0000 0x8800 \
                    0x0226 0x1000 0x0000 0x0010 
#;
#;iprl_magcam_counter
#SETREG R5449 0
tcblock mbipldin    0x0140 0x1549 0x0000 
#=======================================================
#
# File: cam_reg51r_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 14-Oct-1996 18:59:10.00
#; Input File: cam_reg51r_v01.reg
#;
#;
#;iprl_magcam_do_align
#SETREG R5422 0
tcblock mbipldin    0x0140 0x152E 0x0000 
#;
#;iprl_magcam_yalign
#SETREGS R5423   8 1:0x0000  17:0x0000  1024  1966  1024  128
tcblock mbipldin    0x01B2 0x152F 0x0008 0x0000 0x0800 \
                    0x0000 0x8800 0x0400 0x07AE 0x0400 \
                    0x0080 
#;
#;iprl_magcam_move1a
#SETREGS R5431   6 2:0x0226  1:0x0000  0x100000L
tcblock mbipldin    0x01B2 0x1537 0x0006 0x0226 0x1000 \
                    0x0000 0x0800 0x0000 0x0010 
#;
#;iprl_magcam_move1b
#SETREGS R5437   6 2:0x0226  17:0x0000  0x100000L
tcblock mbipldin    0x01B2 0x153D 0x0006 0x0226 0x1000 \
                    0x0000 0x8800 0x0000 0x0010 
#;
#;iprl_magcam_move2
#SETREGS R5443   6 17:0x0000  2:0x0226  0x100000L
tcblock mbipldin    0x01B2 0x1543 0x0006 0x0000 0x8800 \
                    0x0226 0x1000 0x0000 0x0010 
#;
#;iprl_magcam_counter
#SETREG R5449 0
tcblock mbipldin    0x0140 0x1549 0x0000 
#=======================================================
#
# File: cam_reg56_v02.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 11-Dec-1996 22:41:56.00
#; Input File: cam_reg56_v02.reg
#;
#;
#;iprl_ff_back_m1
#SETREGS R5450   6 12:0x00000  13:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x154A 0x0006 0x0000 0x6000 \
                    0x0800 0x6810 0x8000 0x0001 
#;
#;iprl_ff_back_m2
#SETREGS R5456   6 12:0x18000  15:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x1550 0x0006 0x8000 0x6001 \
                    0x0800 0x7810 0x8000 0x0001 
#;
#;iprl_ff_back_m3
#SETREGS R5462   6 12:0x30000  17:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x1556 0x0006 0x0000 0x6003 \
                    0x0800 0x8810 0x8000 0x0001 
#;
#;iprl_ff_back_m4
#SETREGS R5468   6 12:0x48000  18:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x155C 0x0006 0x8000 0x6004 \
                    0x0800 0x9010 0x8000 0x0001 
#;
#;iprl_ff_back_m5
#SETREGS R5474   6 12:0x60000  10:0x080000  0xa0000L
tcblock mbipldin    0x01B2 0x1562 0x0006 0x0000 0x6006 \
                    0x0000 0x5008 0x0000 0x000A 
#;
#;iprl_ff_back_md1
#SETREGS R5480   6 12:0x64000  0:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x1568 0x0006 0x4000 0x6006 \
                    0x7000 0x0010 0x9000 0x0001 
#;
#;iprl_ff_back_md2
#SETREGS R5486   6 12:0x7d000  1:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x156E 0x0006 0xD000 0x6007 \
                    0x7000 0x0810 0x9000 0x0001 
#;
#;iprl_ff_back_md3
#SETREGS R5492   6 12:0x96000  2:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x1574 0x0006 0x6000 0x6009 \
                    0x7000 0x1010 0x9000 0x0001 
#;
#;iprl_ff_back_md4
#SETREGS R5498   6 12:0xaf000  3:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x157A 0x0006 0xF000 0x600A \
                    0x7000 0x1810 0x9000 0x0001 
#;
#;iprl_ff_rest_m1
#SETREGS R5504   6 13:0x100800  10:0x20000  0x18000L
tcblock mbipldin    0x01B2 0x1580 0x0006 0x0800 0x6810 \
                    0x0000 0x5002 0x8000 0x0001 
#;
#;iprl_ff_rest_m2
#SETREGS R5510   6 15:0x100800  10:0x38000  0x18000L
tcblock mbipldin    0x01B2 0x1586 0x0006 0x0800 0x7810 \
                    0x8000 0x5003 0x8000 0x0001 
#;
#;iprl_ff_rest_m3
#SETREGS R5516   6 17:0x100800  10:0x50000  0x18000L
tcblock mbipldin    0x01B2 0x158C 0x0006 0x0800 0x8810 \
                    0x0000 0x5005 0x8000 0x0001 
#;
#;iprl_ff_rest_m4
#SETREGS R5522   6 18:0x100800  10:0x68000  0x18000L
tcblock mbipldin    0x01B2 0x1592 0x0006 0x0800 0x9010 \
                    0x8000 0x5006 0x8000 0x0001 
#;
#;iprl_ff_rest_md1
#SETREGS R5528   6 0:0x107000  10:0x84000  0x19000L
tcblock mbipldin    0x01B2 0x1598 0x0006 0x7000 0x0010 \
                    0x4000 0x5008 0x9000 0x0001 
#;
#;iprl_ff_rest_md2
#SETREGS R5534   6 1:0x107000  10:0x9d000  0x19000L
tcblock mbipldin    0x01B2 0x159E 0x0006 0x7000 0x0810 \
                    0xD000 0x5009 0x9000 0x0001 
#;
#;iprl_ff_rest_md3
#SETREGS R5540   6 2:0x107000  10:0xb6000  0x19000L
tcblock mbipldin    0x01B2 0x15A4 0x0006 0x7000 0x1010 \
                    0x6000 0x500B 0x9000 0x0001 
#;
#;iprl_ff_rest_md4
#SETREGS R5546   6 3:0x107000  10:0xcf000  0x19000L
tcblock mbipldin    0x01B2 0x15AA 0x0006 0x7000 0x1810 \
                    0xF000 0x500C 0x9000 0x0001 
#=======================================================
#
# File: cam_reg61_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  4-Mar-1997 17:37:18.00
#; Input File: cam_reg61_v01.reg
#;
#;
#;iprl_ext_hr_t_ve_le_ce
#SETREGS R5552   6 490000L  700  700  1024  0x2240
tcblock mbipldin    0x01B2 0x15B0 0x0006 0x7A10 0x0007 \
                    0x02BC 0x02BC 0x0400 0x2240 
#=======================================================
#
# File: cam_reg70_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run:  4-Nov-1997 00:56:32.00
#; Input File: cam_reg70_v01.reg
#;
#;
#;iprl_crop_rad504b
#SETREGS R5558   5 14:0x51000  0x07e0  199472L
tcblock mbipldin    0x01B2 0x15B6 0x0005 0x1000 0x7005 \
                    0x07E0 0x0B30 0x0003 
#;
#;iprl_storec2_scale
#SETREGS R5563   8 7:0x000000  19:0x0726  0x100000L  1  15
tcblock mbipldin    0x01B2 0x15BB 0x0008 0x0000 0x3800 \
                    0x0726 0x9800 0x0000 0x0010 0x0001 \
                    0x000F 
#;
#;iprl_storec2_header
#SETREGS R5571   6 19:0x110226  19:0x0500  550L
tcblock mbipldin    0x01B2 0x15C3 0x0006 0x0226 0x9811 \
                    0x0500 0x9800 0x0226 0x0000 
#;
#;iprl_bin_fmt_crop
#SETREGS R5577   8 0:0x0  0:0x0  0:0x0  0:0x0
tcblock mbipldin    0x01B2 0x15C9 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vvcc_p30c
#SETREGS R5585   8 19:0x0726  17:0x0726  18:0x0726  19:0x0726
tcblock mbipldin    0x01B2 0x15D1 0x0008 0x0726 0x9800 \
                    0x0726 0x8800 0x0726 0x9000 0x0726 \
                    0x9800 
#;
#;iprl_vvcc_c30c
#SETREGS R5593   8 5:0x0726  17:0x0726  18:0x0726  5:0x0726
tcblock mbipldin    0x01B2 0x15D9 0x0008 0x0726 0x2800 \
                    0x0726 0x8800 0x0726 0x9000 0x0726 \
                    0x2800 
#;
#;iprl_vvcc_c30v
#SETREGS R5601   8 7:0x0726  17:0x0726  13:0x0726  0:0x0
tcblock mbipldin    0x01B2 0x15E1 0x0008 0x0726 0x3800 \
                    0x0726 0x8800 0x0726 0x6800 0x0000 \
                    0x0000 
#;
#;iprl_ext_hr_t2_ve_fe_me
#SETREGS R5609   6 490000L  700  700  1024  0x2240
tcblock mbipldin    0x01B2 0x15E9 0x0006 0x7A10 0x0007 \
                    0x02BC 0x02BC 0x0400 0x2240 
#=======================================================
#
# File: cam_reg85_v01.src
#
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 30-Mar-1999 20:55:47.00
#; Input File: cam_reg85_v01.reg
#;
#;
#;iprl_crop_rad492
#SETREGS R5615   5 14:0x52000  0x0f60  760476L
tcblock mbipldin    0x01B2 0x15EF 0x0005 0x2000 0x7005 \
                    0x0F60 0x9A9C 0x000B 
#=======================================================
