# File: str_rlinit.src # program "%Z% MODULE: %M% RELEASE: %R%.%L% CREATED: %G% %U%" source "str_rlinit.ips" descr "Loads IP queue instructions" # # DSBQUE ; Disable Queue tcblock mbipldin 0x0154 # #======================================================= # # #;============================================================== #; str_rlinit - Initializes Register lists for structure program #; #; v00 - Dec 96 Dnyanesh Mathur #; #; V01 - 5 Jan 95 Dnyanesh Mathur #; 1. Changed shift count for line depth from 9 to 11 to #; take into account the higher flux seen by the flight #; instrument. Also changed dpc's for Continuum, Mag Proxy #; Flux budget and LOI-c Circular Buffer. #; #;-------------------------------------------------------------- #; #; Regsiter Usage: #; #; Registers Usage #; 168 - 183 Mag Proxy LRDXFR #1 #; 184 - 199 TWAVG #1 #; 200 - 215 TWAVG #2 #; 216 - 223 Copy List to 1 #; 224 - 231 Copy List to 2 #; #; 232 - 247 Flux Budget LRDXFR #1 #; 248 - 263 TWAVG #1 #; 264 - 279 TWAVG #2 #; 280 - 287 Copy List to 1 #; 288 - 295 Copy List to 2 #; #; 296 - 311 Limb Figure LRDXFR #1 #; 312 - 327 TWAVG #1 #; 328 - 343 TWAVG #2 #; 344 - 351 Copy List to 1 #; 352 - 359 Copy List to 2 #; #;-------------------------------------------------------------- #; Register List Assignments: #; #; Register List Length Description #; 1. R728 24 Weight Table used for MP TWA #; 2. R752 24 Weight Table used for FB TWA #; 3. R776 24 Weight Table used for LF TWA #; #; R1024 8 Mag Proxy 1 #; R1032 8 Mag Proxy 2 #; R1040 8 Flux Budget 1 #; R1048 8 Flux Budget 2 #; R1056 8 Limb Figure 1 #; R1064 8 Limb Figure 2 #; R1072 8 Medium-l #; R1080 9 Flat fielding fro FB #; R1092 8 Bad Pix Correction for Med-l #; R1100 9 Flat Field Correction for MP #; #; R1116 5 Copy Vel Table to working area #; R1124 5 Copy Recip Table to working ar #; R1132 8 Velocity Table #; R1140 9 Line Depth Register List #; #; R3040 9 L-Depth Flat Field for Mag Pro #; R3052 8 Bad Pixel correction fro Med-l #; R3060 9 Continuum Flat Field for FB #; #;-------------------------------------------------------------- #; #QSR_STR_RLINIT:: #; # BRANCHIF $IPRF_STR_REGINI &DO_REGINI tcblock mbipcmd 0x0091 0x0600 0x015A 0x05BA 0x0604 # RTNQUE tcblock mbipcmd 0x0091 0x0603 0x01FA #; #;..................................... #; #DO_REGINI: # SETREG $IPRF_STR_REGINI 1 tcblock mbipcmd 0x0091 0x0604 0x0140 0x05BA 0x0001 #; # SETREGS R21 3 0xFFFF 0 0 tcblock mbipcmd 0x0091 0x0607 0x01B2 0x0015 0x0003 0xFFFF \ 0x0000 0x0000 #; #;..................................... #; Velocity Register List: # SETREGS $IPRL_STR_VEL60 8 0:0x00514 1:0x00514 5:0x00000 tcblock mbipcmd 0x0091 0x060D 0x01B2 0x04C7 0x0008 0x0514 \ 0x0000 0x0514 0x0800 0x0000 \ 0x2800 0x0002 0x007F # SETREGS $IPRL_STR_VEL30 8 0:0x00514 1:0x00514 5:0x00000 tcblock mbipcmd 0x0091 0x0618 0x01B2 0x04CF 0x0008 0x0514 \ 0x0000 0x0514 0x0800 0x0000 \ 0x2800 0x0003 0x007F #; #; Line Depth Register List: # SETREGS $IPRL_STR_LD60 9 0:0x00514 1:0x00514 6:0x00000 tcblock mbipcmd 0x0091 0x0623 0x01B2 0x04E1 0x0009 0x0514 \ 0x0000 0x0514 0x0800 0x0000 \ 0x3000 0x0007 0x007F 0x0008 # SETREGS $IPRL_STR_LD30 9 0:0x00514 1:0x00514 6:0x00000 tcblock mbipcmd 0x0091 0x062F 0x01B2 0x04EA 0x0009 0x0514 \ 0x0000 0x0514 0x0800 0x0000 \ 0x3000 0x0007 0x007F 0x0008 #; #; Initalizes Register Sets R168-R231, R232-R295, R296-R359 #; #; Line Depth #; #; LRDXFR R168 #; NpixTotal 0 #; NpixSeg 0 #; Seqment 12 #; Source 14:0xE0000 #; MaxSource 960 #; N 0 #; K 0 #; SegLength 960 #; DPID 0xBFFFFFB1L #; NPixImage 11520L #; #; SETREGS R168 9 0 0 0 12 14:0xC7C00 960 0 0 ; LRDXFR Regis #; SETREGS R177 5 960 0xBFFF 0xFFB1 11520 0 #; #; Initialize registers to create two sets of Time Weighted Averag # SETREGS R728 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x063B 0x01B2 0x02D8 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R736 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x0646 0x01B2 0x02E0 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R744 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x0651 0x01B2 0x02E8 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R184 6 7:0x118000 14:0xC0000 14:0xB0000 tcblock mbipcmd 0x0091 0x065C 0x01B2 0x00B8 0x0006 0x8000 \ 0x3811 0x0000 0x700C 0x0000 \ 0x700B # SETREGS R190 6 0x4000L R728 0 24 16 tcblock mbipcmd 0x0091 0x0665 0x01B2 0x00BE 0x0006 0x4000 \ 0x0000 0x02D8 0x0000 0x0018 \ 0x0010 # SETREGS R200 6 7:0x11C000 14:0xC8000 14:0xB0000 tcblock mbipcmd 0x0091 0x066E 0x01B2 0x00C8 0x0006 0xC000 \ 0x3811 0x8000 0x700C 0x0000 \ 0x700B # SETREGS R206 6 0x4000L R728 12 24 16 tcblock mbipcmd 0x0091 0x0677 0x01B2 0x00CE 0x0006 0x4000 \ 0x0000 0x02D8 0x000C 0x0018 \ 0x0010 #; #; Initialize Registers to copy Commanded LF List to working area #; SETREGS R216 6 14:0x11000 14:0x18000 0x1000L #; SETREGS R224 6 14:0x11000 14:0x1F000 0x1000L #; #; Continuum Intensity #; #; LRDXFR R232 #; NpixTotal 0 #; NpixSeg 0 #; Seqment 12 #; Source 14:0xE2D00 #; MaxSource 960 #; N 0 #; K 0 #; SegLength 960 #; DPID 0xBFFFFFB1L #; NPixImage 11520L #; #; SETREGS R232 9 0 0 0 12 14:0xD8A00 960 0 0 ; LRDXFR Regis #; SETREGS R241 5 960 0xBFFF 0xFFB2 11520 0 #; #; Initialize registers to create two sets of Time Weighted Averag # SETREGS R752 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x0680 0x01B2 0x02F0 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R760 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x068B 0x01B2 0x02F8 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R768 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x0696 0x01B2 0x0300 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R248 6 5:0x118000 14:0xD0000 14:0xB4000 tcblock mbipcmd 0x0091 0x06A1 0x01B2 0x00F8 0x0006 0x8000 \ 0x2811 0x0000 0x700D 0x4000 \ 0x700B # SETREGS R254 6 0x4000L R752 0 24 16 tcblock mbipcmd 0x0091 0x06AA 0x01B2 0x00FE 0x0006 0x4000 \ 0x0000 0x02F0 0x0000 0x0018 \ 0x0010 # SETREGS R264 6 5:0x11C000 14:0xD8000 14:0xB4000 tcblock mbipcmd 0x0091 0x06B3 0x01B2 0x0108 0x0006 0xC000 \ 0x2811 0x8000 0x700D 0x4000 \ 0x700B # SETREGS R270 6 0x4000L R752 12 24 16 tcblock mbipcmd 0x0091 0x06BC 0x01B2 0x010E 0x0006 0x4000 \ 0x0000 0x02F0 0x000C 0x0018 \ 0x0010 #; #; Initialize Registers to copy Commanded LF List to working area #; SETREGS R280 6 14:0x21000 14:0x28000 0x1000L #; SETREGS R288 6 14:0x21000 14:0x16000 0x1000L #; #; Limb Figure #; #; LRDXFR R296 #; NpixTotal 0 #; NpixSeg 0 #; Seqment 12 #; Source 14:0xE5A00 #; MaxSource 1280 #; N 0 #; K 0 #; SegLength 1280 #; DPID 0xBFFFFFB1L #; NPixImage 15360L #; #; SETREGS R296 9 0 0 0 12 14:0xE9800 1280 0 0 ; LRDXFR Regi #; SETREGS R305 5 1280 0xBFFF 0xFFB3 15360 16 #; #; #; Initialize registers to create two sets of Time Weighted Averag # SETREGS R776 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x06C5 0x01B2 0x0308 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R784 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x06D0 0x01B2 0x0310 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R792 8 1 1 1 1 1 1 1 1 tcblock mbipcmd 0x0091 0x06DB 0x01B2 0x0318 0x0008 0x0001 \ 0x0001 0x0001 0x0001 0x0001 \ 0x0001 0x0001 0x0001 # SETREGS R312 6 6:0x110000 14:0xE0000 14:0xB8000 tcblock mbipcmd 0x0091 0x06E6 0x01B2 0x0138 0x0006 0x0000 \ 0x3011 0x0000 0x700E 0x8000 \ 0x700B # SETREGS R318 6 0x5000L R776 0 24 16 tcblock mbipcmd 0x0091 0x06EF 0x01B2 0x013E 0x0006 0x5000 \ 0x0000 0x0308 0x0000 0x0018 \ 0x0010 # SETREGS R328 6 6:0x116000 14:0xEC000 14:0xB8000 tcblock mbipcmd 0x0091 0x06F8 0x01B2 0x0148 0x0006 0x6000 \ 0x3011 0xC000 0x700E 0x8000 \ 0x700B # SETREGS R334 6 0x5000L R776 12 24 16 tcblock mbipcmd 0x0091 0x0701 0x01B2 0x014E 0x0006 0x5000 \ 0x0000 0x0308 0x000C 0x0018 \ 0x0010 #; #; Initialize Registers to copy Commanded LF List to working area # SETREGS R344 6 14:0x01000 14:0x03000 0x2000L tcblock mbipcmd 0x0091 0x070A 0x01B2 0x0158 0x0006 0x1000 \ 0x7000 0x3000 0x7000 0x2000 \ 0x0000 # SETREGS R352 6 14:0x01000 14:0x05000 0x2000L tcblock mbipcmd 0x0091 0x0713 0x01B2 0x0160 0x0006 0x1000 \ 0x7000 0x5000 0x7000 0x2000 \ 0x0000 #; #; Set initial operating parameters #; _COPYLST R216 ;MP RWBIN 1 <-- New MP RWBIN #; _COPYLST R224 ;MP RWBIN 2 <-- New MP RWBIN #; _COPYLST R280 ;FB RWBIN 1 <-- New FB RWBIN #; _COPYLST R288 ;FB RWBIN 2 <-- New FB RWBIN # _COPYLST R344 ; LFCropList1 <- New LF Crop L tcblock mbipcmd 0x0091 0x071C 0x81C2 0x0158 # _COPYLST R352 ; LFCropList1 <- New LF Crop L tcblock mbipcmd 0x0091 0x071E 0x81C2 0x0160 #; # COPYRD2D R168 R374 14 ; L-Depth initial Value Reg Bank -> tcblock mbipcmd 0x0091 0x0720 0x0144 0x00A8 0x0176 0x000E # COPYRD2D R232 R388 14 ; Continuum Intensity register set tcblock mbipcmd 0x0091 0x0724 0x0144 0x00E8 0x0184 0x000E # COPYRD2D R296 R402 14 ; Set LRDXFR from set 1 tcblock mbipcmd 0x0091 0x0728 0x0144 0x0128 0x0192 0x000E #; # COPYRD2D R184 R908 12 ; Reset MP TWA parameter set # tcblock mbipcmd 0x0091 0x072C 0x0144 0x00B8 0x038C 0x000C # COPYRD2D R200 R928 12 ; Reset MP TWA parameter set # tcblock mbipcmd 0x0091 0x0730 0x0144 0x00C8 0x03A0 0x000C # COPYRD2D R248 R960 12 ; Reset FB TWA parameter set # tcblock mbipcmd 0x0091 0x0734 0x0144 0x00F8 0x03C0 0x000C # COPYRD2D R264 R980 12 ; Reset FB TWA parameter set # tcblock mbipcmd 0x0091 0x0738 0x0144 0x0108 0x03D4 0x000C # COPYRD2D R312 R864 12 ; Reset LF TWA parameter set # tcblock mbipcmd 0x0091 0x073C 0x0144 0x0138 0x0360 0x000C # COPYRD2D R328 R888 12 ; Reset LF TWA parameter set # tcblock mbipcmd 0x0091 0x0740 0x0144 0x0148 0x0378 0x000C #; #; Initialize Register Lists #; #; Magnetic Proxy # SETREGS R1024 8 0x0800 7:0x118000 0 50 14:0x11000 R tcblock mbipcmd 0x0091 0x0744 0x01B2 0x0400 0x0008 0x0800 \ 0x8000 0x3811 0x0000 0x0032 \ 0x1000 0x7001 0x0045 # SETREGS R1032 8 0x0800 7:0x11C000 0 50 14:0x11000 R tcblock mbipcmd 0x0091 0x074F 0x01B2 0x0408 0x0008 0x0800 \ 0xC000 0x3811 0x0000 0x0032 \ 0x1000 0x7001 0x0045 # SETREGS R3040 9 6:0x00000 10:0x00000 1:0x00000 0x100000 tcblock mbipcmd 0x0091 0x075A 0x01B2 0x0BE0 0x0009 0x0000 \ 0x3000 0x0000 0x5000 0x0000 \ 0x0800 0x0000 0x0010 0x0010 #; #; Flux Budget # SETREGS R1040 8 0x0800 5:0x118000 0 50 14:0x21000 tcblock mbipcmd 0x0091 0x0766 0x01B2 0x0410 0x0008 0x0800 \ 0x8000 0x2811 0x0000 0x0032 \ 0x1000 0x7002 0x0045 # SETREGS R1048 8 0x0800 5:0x11C000 0 50 14:0x21000 tcblock mbipcmd 0x0091 0x0771 0x01B2 0x0418 0x0008 0x0800 \ 0xC000 0x2811 0x0000 0x0032 \ 0x1000 0x7002 0x0045 # SETREGS R3060 9 7:0x00000 10:0x000000 1:0x00000 0x10000 tcblock mbipcmd 0x0091 0x077C 0x01B2 0x0BF4 0x0009 0x0000 \ 0x3800 0x0000 0x5000 0x0000 \ 0x0800 0x0000 0x0010 0x0010 #; #; Limb Figure #; SETREGS R1056 8 0x5800 6:0x110000 0 2000 14:0x0300 # SETREGS R1056 8 0x3800 6:0x110000 0 2000 14:0x0300 tcblock mbipcmd 0x0091 0x0788 0x01B2 0x0420 0x0008 0x3800 \ 0x0000 0x3011 0x0000 0x07D0 \ 0x3000 0x7000 0x0045 #; SETREGS R1064 8 0x5000 6:0x116000 0 2000 14:0x0500 # SETREGS R1064 8 0x3800 6:0x116000 0 2000 14:0x0500 tcblock mbipcmd 0x0091 0x0793 0x01B2 0x0428 0x0008 0x3800 \ 0x6000 0x3011 0x0000 0x07D0 \ 0x5000 0x7000 0x0045 #; #; Medium-l #; SETREGS R1072 8 0x2800 7:0x110000 0 0x0006 14:0x0700 # SETREGS R1072 8 0x0800 7:0x110000 0 0x0006 14:0x0700 tcblock mbipcmd 0x0091 0x079E 0x01B2 0x0430 0x0008 0x0800 \ 0x0000 0x3811 0x0000 0x0006 \ 0x7000 0x7000 0x0045 # SETREGS R3052 8 5:0x00000 10:0x00000 1:0x00000 0x100000 tcblock mbipcmd 0x0091 0x07A9 0x01B2 0x0BEC 0x0008 0x0000 \ 0x2800 0x0000 0x5000 0x0000 \ 0x0800 0x0000 0x0010 #; #; #; Register lists for copying Reciprocal and Velocity #; tables to working area # SETREGS R1116 5 0x0000 0x000B 0x8000 0x800A 4 tcblock mbipcmd 0x0091 0x07B4 0x01B2 0x045C 0x0005 0x0000 \ 0x000B 0x8000 0x800A 0x0004 # SETREGS R1124 5 0x8000 0x0009 0x0000 0x800A 4 tcblock mbipcmd 0x0091 0x07BC 0x01B2 0x0464 0x0005 0x8000 \ 0x0009 0x0000 0x800A 0x0004 #; #; Register List for Error log dump # SETREGS R460 9 0 0 0 1 4:0x110000 4800 0 0 tcblock mbipcmd 0x0091 0x07C4 0x01B2 0x01CC 0x0009 0x0000 \ 0x0000 0x0000 0x0001 0x0000 \ 0x2011 0x12C0 0x0000 0x0000 # SETREGS R469 5 4800 0x2E00 0x0000 4800 0 tcblock mbipcmd 0x0091 0x07D0 0x01B2 0x01D5 0x0005 0x12C0 \ 0x2E00 0x0000 0x12C0 0x0000 #; #; Register Dump data product # SETREGS $IPRL_STR_RDUMP 6 0 0 0 1 7:0x113C00 tcblock mbipcmd 0x0091 0x07D8 0x01B2 0x047A 0x0006 0x0000 \ 0x0000 0x0000 0x0001 0x3C00 \ 0x3811 # SETREGS $IPRL_STR_RDUMP+6 6 94 0 0 94 0x2000 0x0000 tcblock mbipcmd 0x0091 0x07E1 0x01B2 0x0480 0x0006 0x005E \ 0x0000 0x0000 0x005E 0x2000 \ 0x0000 # SETREGS $IPRL_STR_RDUMP+12 2 94 0 tcblock mbipcmd 0x0091 0x07EA 0x01B2 0x0486 0x0002 0x005E \ 0x0000 #; # SETREGS $IPRL_STR_MKLOIV 8 0x2800 7:0x114740 0 45 14:0x03400 tcblock mbipcmd 0x0091 0x07EF 0x01B2 0x048C 0x0008 0x2800 \ 0x4740 0x3811 0x0000 0x002D \ 0x4000 0x7003 0x0045 # SETREGS $IPRL_STR_MKLOIC 8 0x3800 5:0x114920 0 45 14:0x03000 tcblock mbipcmd 0x0091 0x07FA 0x01B2 0x0494 0x0008 0x3800 \ 0x4920 0x2811 0x0000 0x002D \ 0x0000 0x7003 0x0045 #; #; LOI -> Circ. Buff. Copy # SETREGS $IPRL_STR_LOIC2CB 8 5:0x11491C 12:0x010230 184L tcblock mbipcmd 0x0091 0x0805 0x01B2 0x05AA 0x0008 0x491C \ 0x2811 0x0230 0x6001 0x00B8 \ 0x0000 0x0000 0x04B0 # SETREGS $IPRL_STR_LOIV2CB 8 7:0x11473C 12:0x050230 184L tcblock mbipcmd 0x0091 0x0810 0x01B2 0x05B2 0x0008 0x473C \ 0x3811 0x0230 0x6005 0x00B8 \ 0x0000 0x0000 0x04B0 # # SETREGS R562 2 0x20000L tcblock mbipcmd 0x0091 0x081B 0x01B2 0x0232 0x0002 0x0000 \ 0x0002 #; #; HRDINIT Register Lists # SETREGS $IPRL_STR_V60HDR 6 0:0x00001 0x2000 0xE4 0x42 tcblock mbipcmd 0x0091 0x0820 0x01B2 0x05E8 0x0006 0x0001 \ 0x0000 0x2000 0x00E4 0x4200 \ 0x0FC0 # SETREGS $IPRL_STR_V30HDR 6 0:0x00001 0x2000 0xE4 0x42 tcblock mbipcmd 0x0091 0x0829 0x01B2 0x05F0 0x0006 0x0001 \ 0x0000 0x2000 0x00E4 0x4240 \ 0x0FC0 # SETREGS $IPRL_STR_IC60HDR 6 0:0x00001 0x2000 0xE2 0x46 tcblock mbipcmd 0x0091 0x0832 0x01B2 0x05F8 0x0006 0x0001 \ 0x0000 0x2000 0x00E2 0x4601 \ 0x0FC0 # SETREGS $IPRL_STR_IC30HDR 6 0:0x00001 0x2000 0xE2 0x46 tcblock mbipcmd 0x0091 0x083B 0x01B2 0x0600 0x0006 0x0001 \ 0x0000 0x2000 0x00E2 0x4641 \ 0x0FC0 # SETREGS $IPRL_STR_CBVHDR 6 4:0x00001 0x3000 0 0x43 tcblock mbipcmd 0x0091 0x0844 0x01B2 0x065C 0x0006 0x0001 \ 0x2000 0x3000 0x0000 0x43C0 \ 0x9001 # SETREGS $IPRL_STR_CBIHDR 6 4:0x00001 0x3000 0 0x47 tcblock mbipcmd 0x0091 0x084D 0x01B2 0x0662 0x0006 0x0001 \ 0x2000 0x3000 0x0000 0x47C1 \ 0x9001 #; #; Continuum Register Lists # SETREGS $IPRL_STR_EXTRSD 8 2:0x00514 1:0x00000 1024 1024 1 tcblock mbipcmd 0x0091 0x0856 0x01B2 0x0618 0x0008 0x0514 \ 0x1000 0x0000 0x0800 0x0400 \ 0x0400 0x0410 0x0045 # SETREGS $IPRL_STR_EXTRSI 8 3:0x00514 4:0x00226 1024 1024 1 tcblock mbipcmd 0x0091 0x0861 0x01B2 0x0620 0x0008 0x0514 \ 0x1800 0x0226 0x2000 0x0400 \ 0x0400 0x0410 0x0045 # SETREGS $IPRL_STR_MKIC 8 4:0x00226 6:0x00000 1:0x00000 7 tcblock mbipcmd 0x0091 0x086C 0x01B2 0x0628 0x0008 0x0226 \ 0x2000 0x0000 0x3000 0x0000 \ 0x0800 0x0000 0x3800 # SETREGS $IPRL_STR_MKIC+8 2 63 200 tcblock mbipcmd 0x0091 0x0877 0x01B2 0x0630 0x0002 0x003F \ 0x00C8 #; # RTNQUE tcblock mbipcmd 0x0091 0x087C 0x01FA #; #; #; #;................................................................ #; #; #; 5k Data: #; Medium-l 80% 15360 #; Limb Figure 5% 960 (Time Wtd. Avg) #; Line Depth 5% 960 ( " " " ) #; Continuum 5% 960 ( " " " ) #; LOI-V 2.5% 480 #; LOI-C 2.5% 480 #; #; #; Map of List Memory: #; #; Address Range Description #; 14:0x000000 Full Disk Crop List #; 14:0x001000 Limb Figure Crop List #; 14:0x003000 LF List #1 #; 14:0x005000 LF List #2 #; 14:0x007000 Vector Weighted Bin List (Med-l) #; 14:0x011000 Rectangular Weighted Bin List (Mag P #; 14:0x021000 RWBin List (Flux Budget) #; #; 14:0x0C7C00 Line Depth Output Buffer #1 #; 14:0x0CA900 Line Depth Accumulation Buffer #1 #; 14:0x0D0300 Line Depth Output Buffer #2 #; 14:0x0D3000 Line Depth Accumulation Buffer #2 #; 14:0x0D8A00 Continuum Intensity Output Buffer #1 #; 14:0x0DB700 Continuum Intensity Acc. Buffer #1 #; 14:0x0E1100 Continuum Intensity Output Buffer #2 #; 14:0x0E3E00 Continuum Intensity Acc. Buffer #2 #; 14:0x0E9800 Limb Figure Output Buffer #1 #; 14:0x0ED400 Limb Figure Acc. Buffer #1 #; 14:0x0F4C00 Limb Figure Output Buffer #2 #; 14:0x0F8800 Limb Figure Acc. Buffer #2 #; #; 2 Mar 95: Use a single output buffer for TWA DP.'s. #; 6 Mar 95: Reassigned Register banks to eliminate 2nd LRDXFR #; Assigned List copying registers to start at #; 4 Register boundry. #;........................................................... #; #QSR_STR_DAINIT:: #; #; #; Initilization #; # FILLBLK 7:0x110000 15360L 0xA123 ; Med-l data block tcblock mbipcmd 0x0091 0x087D 0x016C 0x0000 0x3811 0x3C00 \ 0x0000 0xA123 # FILLBLK 7:0x113C00 960L 0xB456 tcblock mbipcmd 0x0091 0x0883 0x016C 0x3C00 0x3811 0x03C0 \ 0x0000 0xB456 # FILLBLK 7:0x113FC0 960L 0xC789 tcblock mbipcmd 0x0091 0x0889 0x016C 0x3FC0 0x3811 0x03C0 \ 0x0000 0xC789 # FILLBLK 7:0x114380 960L 0x0D23 tcblock mbipcmd 0x0091 0x088F 0x016C 0x4380 0x3811 0x03C0 \ 0x0000 0x0D23 # FILLBLK 7:0x114740 480L 0x0E45 tcblock mbipcmd 0x0091 0x0895 0x016C 0x4740 0x3811 0x01E0 \ 0x0000 0x0E45 # FILLBLK 7:0x114920 480L 0x0F67 tcblock mbipcmd 0x0091 0x089B 0x016C 0x4920 0x3811 0x01E0 \ 0x0000 0x0F67 # FILLBLK 13:0x000000 0x100000L 0x0001 tcblock mbipcmd 0x0091 0x08A1 0x016C 0x0000 0x6800 0x0000 \ 0x0010 0x0001 # SETREGS R1016 6 13:0x000000 10:0x000000 0x100000L tcblock mbipcmd 0x0091 0x08A7 0x01B2 0x03F8 0x0006 0x0000 \ 0x6800 0x0000 0x5000 0x0000 \ 0x0010 # DAT2LST R1016 tcblock mbipcmd 0x0091 0x08B0 0x01C4 0x03F8 #; #; #; The accumulation and output buffers for Time Weighted Averages #; in a List memory Page (8 byte EDAC). #; #; Line Depth Telemetry buffer #; FILLBLK 14:0xC7C00 960L 0x3300 #; FILLBLK 14:0xC7FC0 960L 0x3310 #; FILLBLK 14:0xC8380 960L 0x3320 #; FILLBLK 14:0xC8740 960L 0x3330 #; FILLBLK 14:0xC8B00 960L 0x3340 #; FILLBLK 14:0xC8EC0 960L 0x3350 #; FILLBLK 14:0xC9280 960L 0x3360 #; FILLBLK 14:0xC9640 960L 0x3370 #; FILLBLK 14:0xC9A00 960L 0x3380 #; FILLBLK 14:0xC9DC0 960L 0x3390 #; FILLBLK 14:0xCA180 960L 0x33A0 #; FILLBLK 14:0xCA540 960L 0x33B0 #; #; FILLBLK 14:0xD0300 960L 0x3301 #; FILLBLK 14:0xD06C0 960L 0x3311 #; FILLBLK 14:0xD0A80 960L 0x3321 #; FILLBLK 14:0xD0E40 960L 0x3331 #; FILLBLK 14:0xD1200 960L 0x3341 #; FILLBLK 14:0xD15C0 960L 0x3351 #; FILLBLK 14:0xD1980 960L 0x3361 #; FILLBLK 14:0xD1D40 960L 0x3371 #; FILLBLK 14:0xD2100 960L 0x3381 #; FILLBLK 14:0xD24C0 960L 0x3391 #; FILLBLK 14:0xD2880 960L 0x33A1 #; FILLBLK 14:0xD2C40 960L 0x33B1 #; #; Continuum Intensity Telemetry Buffer #; FILLBLK 14:0xD8A00 960L 0x4400 #; FILLBLK 14:0xD8DC0 960L 0x4410 #; FILLBLK 14:0xD9180 960L 0x4420 #; FILLBLK 14:0xD9540 960L 0x4430 #; FILLBLK 14:0xD9900 960L 0x4440 #; FILLBLK 14:0xD9CC0 960L 0x4450 #; FILLBLK 14:0xDA080 960L 0x4460 #; FILLBLK 14:0xDA440 960L 0x4470 #; FILLBLK 14:0xDA800 960L 0x4480 #; FILLBLK 14:0xDABC0 960L 0x4490 #; FILLBLK 14:0xDAF80 960L 0x44A0 #; FILLBLK 14:0xDB340 960L 0x44B0 #; #; FILLBLK 14:0xE1100 960L 0x4401 #; FILLBLK 14:0xE14C0 960L 0x4411 #; FILLBLK 14:0xE1880 960L 0x4421 #; FILLBLK 14:0xE1C40 960L 0x4431 #; FILLBLK 14:0xE2000 960L 0x4441 #; FILLBLK 14:0xE23C0 960L 0x4451 #; FILLBLK 14:0xE2780 960L 0x4461 #; FILLBLK 14:0xE2B40 960L 0x4471 #; FILLBLK 14:0xE2F00 960L 0x4481 #; FILLBLK 14:0xE32C0 960L 0x4491 #; FILLBLK 14:0xE3680 960L 0x44A1 #; FILLBLK 14:0xE3A40 960L 0x44B1 #; #; Limb Figure Telemetry Buffer #1 #; FILLBLK 14:0xE9800 1280L 0x5500 #; FILLBLK 14:0xE9D00 1280L 0x5510 #; FILLBLK 14:0xEA200 1280L 0x5520 #; FILLBLK 14:0xEA700 1280L 0x5530 #; FILLBLK 14:0xEAC00 1280L 0x5540 #; FILLBLK 14:0xEB100 1280L 0x5550 #; FILLBLK 14:0xEB600 1280L 0x5560 #; FILLBLK 14:0xEBB00 1280L 0x5570 #; FILLBLK 14:0xEC000 1280L 0x5580 #; FILLBLK 14:0xEC500 1280L 0x5590 #; FILLBLK 14:0xECA00 1280L 0x55A0 #; FILLBLK 14:0xECF00 1280L 0x55B0 #; #; Limb Figure Telemetry Buffer #2 #; FILLBLK 14:0xF4C00 1280L 0x6601 #; FILLBLK 14:0xF5100 1280L 0x6611 #; FILLBLK 14:0xF5600 1280L 0x6621 #; FILLBLK 14:0xF5B00 1280L 0x6631 #; FILLBLK 14:0xF6000 1280L 0x6641 #; FILLBLK 14:0xF6500 1280L 0x6651 #; FILLBLK 14:0xF6A00 1280L 0x6661 #; FILLBLK 14:0xF6F00 1280L 0x6671 #; FILLBLK 14:0xF7400 1280L 0x6681 #; FILLBLK 14:0xF7900 1280L 0x6691 #; FILLBLK 14:0xF7E00 1280L 0x66A1 #; FILLBLK 14:0xF8300 1280L 0x66B1 #; #; Clear TWA Accumulation Buffers # FILLBLK 0:0x00000 0x100000L 0 ; P0 <= 0 tcblock mbipcmd 0x0091 0x08B2 0x016C 0x0000 0x0000 0x0000 \ 0x0010 0x0000 # SETREGS R500 6 0:0x00000 14:0xB0000 0x38200L ; P0 -> P1 tcblock mbipcmd 0x0091 0x08B8 0x01B2 0x01F4 0x0006 0x0000 \ 0x0000 0x0000 0x700B 0x8200 \ 0x0003 # DAT2LST R500 tcblock mbipcmd 0x0091 0x08C1 0x01C4 0x01F4 #; # RTNQUE tcblock mbipcmd 0x0091 0x08C3 0x01FA #; #;============================================================ #======================================================= # # ENBQUE ; Enable Queue tcblock mbipldin 0x0136 # # return # #=======================================================