# File: cam_reg42_v01.src
#
program "%Z% MODULE: %M% RELEASE: %R%.%L% CREATED: %G% %U%"
source "/mdisw/cfl/prep/src/cam_reg42_v01.src"
descr "Loads IP queue instructions"
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 25-Jul-1996 14:34:38.00
#; Input File: cam_reg42_v01.reg
#;
#;
#;iprl_crop_param (first half)
#SETREGS R5226   4 0:0x0  0:0x0
tcblock mbipldin    0x01B2 0x146A 0x0004 0x0000 0x0000 \
                    0x0000 0x0000 
#;
#;iprl_crop_param (second half)
#SETREGS R5230   5 0:0x0  0  0L
tcblock mbipldin    0x01B2 0x146E 0x0005 0x0000 0x0000 \
                    0x0000 0x0000 0x0000 
#;
#;iprl_crop_offset
#SETREGS R5235   2 0  0
tcblock mbipldin    0x01B2 0x1473 0x0002 0x0000 0x0000 
#;
#;iprl_crop_instr
#SETREGS R5237   8 0  0  0  0  1024  0  0          5235
tcblock mbipldin    0x01B2 0x1475 0x0008 0x0000 0x0000 \
                    0x0000 0x0000 0x0400 0x0000 0x0000 \
                    0x1473 
#;
#;iprl_crop_rad504
#SETREGS R5245   5 14:0x00000  0x0fc0  798020L
tcblock mbipldin    0x01B2 0x147D 0x0005 0x0000 0x7000 \
                    0x0FC0 0x2D44 0x000C 
#;
#;iprl_crop_rad480
#SETREGS R5250   5 14:0x50000  0x0f00  723816L
tcblock mbipldin    0x01B2 0x1482 0x0005 0x0000 0x7005 \
                    0x0F00 0x0B68 0x000B 
#;
#;iprl_vlcm_cont_flt
#SETREGS R5255   3 0  0  0
tcblock mbipldin    0x01B2 0x1487 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_cont
#SETREGS R5258   3 0  0  0
tcblock mbipldin    0x01B2 0x148A 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_vel
#SETREGS R5261   3 0  0  0
tcblock mbipldin    0x01B2 0x148D 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_ldepth
#SETREGS R5264   3 0  0  0
tcblock mbipldin    0x01B2 0x1490 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_vlcm_mag
#SETREGS R5267   3 0  0  0
tcblock mbipldin    0x01B2 0x1493 0x0003 0x0000 0x0000 \
                    0x0000 
#;
#;iprl_store_scale
#SETREGS R5270   8 5:0x000000  15:0x0726  0x100000L  1  13
tcblock mbipldin    0x01B2 0x1496 0x0008 0x0000 0x2800 \
                    0x0726 0x7800 0x0000 0x0010 0x0001 \
                    0x000D 
#;
#;iprl_store_header
#SETREGS R5278   6 19:0x110000  15:0x0500  550L
tcblock mbipldin    0x01B2 0x149E 0x0006 0x0000 0x9811 \
                    0x0500 0x7800 0x0226 0x0000 
#;
#;iprl_storev_scale
#SETREGS R5284   8 5:0x000000  15:0x0726  0x100000L  1  13
tcblock mbipldin    0x01B2 0x14A4 0x0008 0x0000 0x2800 \
                    0x0726 0x7800 0x0000 0x0010 0x0001 \
                    0x000D 
#;
#;iprl_storev_header
#SETREGS R5292   6 19:0x110000  15:0x0500  550L
tcblock mbipldin    0x01B2 0x14AC 0x0006 0x0000 0x9811 \
                    0x0500 0x7800 0x0226 0x0000 
#;
#;iprl_storec_scale
#SETREGS R5298   8 7:0x000000  15:0x0726  0x100000L  1  16
tcblock mbipldin    0x01B2 0x14B2 0x0008 0x0000 0x3800 \
                    0x0726 0x7800 0x0000 0x0010 0x0001 \
                    0x0010 
#;
#;iprl_storec_header
#SETREGS R5306   6 19:0x110226  15:0x0500  550L
tcblock mbipldin    0x01B2 0x14BA 0x0006 0x0226 0x9811 \
                    0x0500 0x7800 0x0226 0x0000 
#;
#;iprl_store_move2
#SETREGS R5312   6 15:0x000500  11:0x0500  0x100226L
tcblock mbipldin    0x01B2 0x14C0 0x0006 0x0500 0x7800 \
                    0x0500 0x5800 0x0226 0x0010 
#;
#;iprl_sqrt_dpc_low
#SETREG R5318 0
tcblock mbipldin    0x0140 0x14C6 0x0000 
#;
#;iprl_std_fmt_vel
#SETREGS R5319   4 7:0x0726  13:0x0726
tcblock mbipldin    0x01B2 0x14C7 0x0004 0x0726 0x3800 \
                    0x0726 0x6800 
#;
#;iprl_std_fmt_ldep
#SETREGS R5323   4 6:0x0726  4:0x0226
tcblock mbipldin    0x01B2 0x14CB 0x0004 0x0726 0x3000 \
                    0x0226 0x2000 
#;
#;iprl_std_fmt_cont
#SETREGS R5327   4 5:0x0726  4:0x0226
tcblock mbipldin    0x01B2 0x14CF 0x0004 0x0726 0x2800 \
                    0x0226 0x2000 
#;
#;iprl_std_fmt_contf
#SETREGS R5331   4 19:0x0726  4:0x0226
tcblock mbipldin    0x01B2 0x14D3 0x0004 0x0726 0x9800 \
                    0x0226 0x2000 
#;
#;iprl_std_fmt_mag
#SETREGS R5335   4 17:0x0726  18:0x0726
tcblock mbipldin    0x01B2 0x14D7 0x0004 0x0726 0x8800 \
                    0x0726 0x9000 
#;
#;iprl_std_fmt_pcont
#SETREGS R5339   4 11:0x0726  18:0x0726
tcblock mbipldin    0x01B2 0x14DB 0x0004 0x0726 0x5800 \
                    0x0726 0x9000 
#;
#;iprl_std_fmt_pvel
#SETREGS R5343   4 11:0x0726  15:0x0726
tcblock mbipldin    0x01B2 0x14DF 0x0004 0x0726 0x5800 \
                    0x0726 0x7800 
#;
#;iprl_extract_50k
#SETREGS R5347   6 512000L  1024  500  1024  0x2d00
tcblock mbipldin    0x01B2 0x14E3 0x0006 0xD000 0x0007 \
                    0x0400 0x01F4 0x0400 0x2D00 
#;
#;iprl_extract_85k
#SETREGS R5353   6 870400L  1024  850  1024  0x2f00
tcblock mbipldin    0x01B2 0x14E9 0x0006 0x4800 0x000D \
                    0x0400 0x0352 0x0400 0x2F00 
#;
#;iprl_extract_75k
#SETREGS R5359   6 768000L  1024  750  1024  0x2040
tcblock mbipldin    0x01B2 0x14EF 0x0006 0xB800 0x000B \
                    0x0400 0x02EE 0x0400 0x2040 
#;
#;iprl_extract_70k
#SETREGS R5365   6 716800L  1024  700  1024  0x2140
tcblock mbipldin    0x01B2 0x14F5 0x0006 0xF000 0x000A \
                    0x0400 0x02BC 0x0400 0x2140 
#=======================================================
#
return
#
#=======================================================
