# File: cam_reg56_v02.src
#
program "%Z% MODULE: %M% RELEASE: %R%.%L% CREATED: %G% %U%"
source "/mdisw/cfl/prep/src/cam_reg56_v02.src"
descr "Loads IP queue instructions"
#=======================================================
#
#
#; OPSDB_MK_REG_IPS Program Run: 11-Dec-1996 22:41:56.00
#; Input File: cam_reg56_v02.reg
#;
#;
#;iprl_ff_back_m1
#SETREGS R5450   6 12:0x00000  13:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x154A 0x0006 0x0000 0x6000 \
                    0x0800 0x6810 0x8000 0x0001 
#;
#;iprl_ff_back_m2
#SETREGS R5456   6 12:0x18000  15:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x1550 0x0006 0x8000 0x6001 \
                    0x0800 0x7810 0x8000 0x0001 
#;
#;iprl_ff_back_m3
#SETREGS R5462   6 12:0x30000  17:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x1556 0x0006 0x0000 0x6003 \
                    0x0800 0x8810 0x8000 0x0001 
#;
#;iprl_ff_back_m4
#SETREGS R5468   6 12:0x48000  18:0x100800  0x18000L
tcblock mbipldin    0x01B2 0x155C 0x0006 0x8000 0x6004 \
                    0x0800 0x9010 0x8000 0x0001 
#;
#;iprl_ff_back_m5
#SETREGS R5474   6 12:0x60000  10:0x080000  0xa0000L
tcblock mbipldin    0x01B2 0x1562 0x0006 0x0000 0x6006 \
                    0x0000 0x5008 0x0000 0x000A 
#;
#;iprl_ff_back_md1
#SETREGS R5480   6 12:0x64000  0:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x1568 0x0006 0x4000 0x6006 \
                    0x7000 0x0010 0x9000 0x0001 
#;
#;iprl_ff_back_md2
#SETREGS R5486   6 12:0x7d000  1:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x156E 0x0006 0xD000 0x6007 \
                    0x7000 0x0810 0x9000 0x0001 
#;
#;iprl_ff_back_md3
#SETREGS R5492   6 12:0x96000  2:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x1574 0x0006 0x6000 0x6009 \
                    0x7000 0x1010 0x9000 0x0001 
#;
#;iprl_ff_back_md4
#SETREGS R5498   6 12:0xaf000  3:0x107000  0x19000L
tcblock mbipldin    0x01B2 0x157A 0x0006 0xF000 0x600A \
                    0x7000 0x1810 0x9000 0x0001 
#;
#;iprl_ff_rest_m1
#SETREGS R5504   6 13:0x100800  10:0x20000  0x18000L
tcblock mbipldin    0x01B2 0x1580 0x0006 0x0800 0x6810 \
                    0x0000 0x5002 0x8000 0x0001 
#;
#;iprl_ff_rest_m2
#SETREGS R5510   6 15:0x100800  10:0x38000  0x18000L
tcblock mbipldin    0x01B2 0x1586 0x0006 0x0800 0x7810 \
                    0x8000 0x5003 0x8000 0x0001 
#;
#;iprl_ff_rest_m3
#SETREGS R5516   6 17:0x100800  10:0x50000  0x18000L
tcblock mbipldin    0x01B2 0x158C 0x0006 0x0800 0x8810 \
                    0x0000 0x5005 0x8000 0x0001 
#;
#;iprl_ff_rest_m4
#SETREGS R5522   6 18:0x100800  10:0x68000  0x18000L
tcblock mbipldin    0x01B2 0x1592 0x0006 0x0800 0x9010 \
                    0x8000 0x5006 0x8000 0x0001 
#;
#;iprl_ff_rest_md1
#SETREGS R5528   6 0:0x107000  10:0x84000  0x19000L
tcblock mbipldin    0x01B2 0x1598 0x0006 0x7000 0x0010 \
                    0x4000 0x5008 0x9000 0x0001 
#;
#;iprl_ff_rest_md2
#SETREGS R5534   6 1:0x107000  10:0x9d000  0x19000L
tcblock mbipldin    0x01B2 0x159E 0x0006 0x7000 0x0810 \
                    0xD000 0x5009 0x9000 0x0001 
#;
#;iprl_ff_rest_md3
#SETREGS R5540   6 2:0x107000  10:0xb6000  0x19000L
tcblock mbipldin    0x01B2 0x15A4 0x0006 0x7000 0x1010 \
                    0x6000 0x500B 0x9000 0x0001 
#;
#;iprl_ff_rest_md4
#SETREGS R5546   6 3:0x107000  10:0xcf000  0x19000L
tcblock mbipldin    0x01B2 0x15AA 0x0006 0x7000 0x1810 \
                    0xF000 0x500C 0x9000 0x0001 
#=======================================================
#
return
#
#=======================================================
